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| * | ARM: dts: exynos4: use the node's name for i2cJaehoon Chung2017-01-18-8/+19
| | | | | | | | | | | | | | | | | | | | | Use the node's name for i2c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | board: samsung: goni: fix the pmic's name for gettingJaehoon Chung2017-01-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Getting from uclass, use the "max8998-pmic" as name. It also needs to change the dt-node's name as "max8998-pmic". Otherwise, it doesn't find the pmic device. Because it's only searching for 'max8998_pmic'. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | ARM: uniphier: move SBC and Support Card init code to U-Boot properMasahiro Yamada2017-01-18-27/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize SBC and Support Card in U-Boot proper instead of SPL. We may run different firmware (ex. ARM Trusted Firmware) before U-Boot, and basic SoC initialization may be done there. In that case, SPL may not be used. The motivation for preparing SBC and Support Card in SPL was to use LED for early debugging, but this is not mandatory to boot SoCs. With this commit, LED will be unavailable in SPL, but we can use a debug serial instead. So, this change will not be a big deal. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: refactor spl_init_board()Masahiro Yamada2017-01-18-508/+250
| | | | | | | | | | | | | | | | | | | | | Merge init-*.c into a single file using a table of callbacks because the initialization flow is almost common among SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: refactor board_init()Masahiro Yamada2017-01-18-95/+141
| | | | | | | | | | | | | | | | | | | | | The code here is cluttered due to the switch statement. Introduce a table of callbacks to clean up the initialization code across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: make BCU init into void functionMasahiro Yamada2017-01-17-10/+10
| | | | | | | | | | | | | | | | | | These functions never fail, so no need to return a value. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: refactor Support Card init codeMasahiro Yamada2017-01-17-28/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Splitting reset assertion (support_card_reset) and deassertion (support_card_init) is not adding much value any more. Handle all the initialization of Support Card in support_card_init(), then remove support_card_reset(). Also, detect_num_flash_banks() can have a static qualifier. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: refactor SBC init codeMasahiro Yamada2017-01-17-110/+94
| | | | | | | | | | | | | | | | | | | | | Merge sbc-admulti.c and sbc-savepin.c into a single file to avoid code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: refactor MEMCONF init codeMasahiro Yamada2017-01-17-259/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code. There are 3 patterns in terms of MEMCONF init: - DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11 - DRAM 3 channels: sLD3 - DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20 All of them can be moved into a single file by a little more refactoring. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: split out UMC clock enableMasahiro Yamada2017-01-17-69/+97
| | | | | | | | | | | | | | | | | | | | | | | | The clock enable bits for UMC are more SoC-specific than for the other hardware blocks. Separate the UMC clocks and the other clocks for better code reuse across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: remove unneeded argument of uniphier_ld20_pll_init()Masahiro Yamada2017-01-17-11/+3
| | | | | | | | | | | | | | | | | | | | | At first, we thought the LD20 PLL setting would be board dependent, but this argument turned out unneeded after all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: dts: uniphier: add UniPhier specific compatible to eMMC nodeMasahiro Yamada2017-01-17-4/+2
| | | | | | | | | | | | | | | | | | | | | The "cdns,sd4hc" is a fallback of the IP. Add the SoC-specific compatible string. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-01-15-0/+166
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| * | | sunxi: dts: OrangePi Zero: add Ethernet nodeAndre Przywara2017-01-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OrangePi Zero can happily use the EMAC along with its integrated PHY to use Ethernet (for TFTP booting, for instance). Add the emac node to the board .dts by copying it from the OrangePi One DT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | sunxi: add proper device tree for Orange Pi Zero boardsIcenowy Zheng2017-01-15-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a proper device tree file for Orange Pi Zero boards from Xunlong, which come with a Allwinner H2+ SoC (similar to H3). Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | sunxi: enable H3 EMAC for the nanopi neoJelle van der Waa2017-01-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nanopi already had the CONFIG_SUN8I_EMAC=y enabled in it's defconfig file, but was missing the &emac the device tree entry. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | | davinci: spl: use bootcfg to select boot deviceFabien Parent2017-01-14-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now the SPL is trying to load u-boot based on defines, i.e. one has to define CONFIG_SPL_NAND_SIMPLE to boot from NAND, or CONFIG_SPL_SPI_LOAD to boot from SPI FLASH, etc... This prevent us from having a single SPL image that is able to boot from all media, and one need to build an image for each medium. This commit is replacing the #ifdef that select the boot medium by reading the value of the boot pins (via the BOOTCFG register). Now a single SPL image will be able to read from the boot pin to know which device should be used to load u-boot. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | armv8: fix #if around spin-table code in start.SOded Gabbay2017-01-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined(). It also adds "&& !defined(CONFIG_SPL_BUILD)" to that #if statement because the spin-table code can't currently work in SPL, and the spin-table file isn't even compiled in SPL. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
* | | | arm: omap-common: add secure ROM signature verify index for AM33xxAndrew F. Davis2017-01-14-0/+4
|/ / / | | | | | | | | | | | | | | | | | | On AM33xx devices the secure ROM uses a different call index for signature verification, the function and arguments are the same. Signed-off-by: Andrew F. Davis <afd@ti.com>
* | | arm: Re-sync asm/mach-types.h with Linux Kernel v4.9Tom Rini2017-01-14-13688/+486
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This re-syncs the MACH_TYPE_xxx values from the Linux Kernel v4.9 release. In addition this removes all of the machine_arch_type and machine_is_xxx logic that is unused in U-Boot. This removal removes a large number of otherwise unused CONFIG values from the list to be converted. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Adam Ford <aford173@gmail.com>
* | | rockchip: rk3288: set isp/vop qos priority levelNickey Yang Nickey Yang2017-01-11-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Isp-camera preview image will be broken when dual screen display mode. This patch set isp/vop qos level higher to solve this problem. We have verified this patch on rk3288-miniarm board. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
* | | arm64: rk3399: update rockchip_get_cru APIKever Yang2017-01-11-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | rk3399 has two clock-controller: cru and pmucru, update the rockchip_get_crui() API, and rockchip_get_clk() do not used for other module. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | | dts: arm64: rk3399: add max-frequency for sdhciKever Yang2017-01-11-0/+1
| | | | | | | | | | | | | | | | | | | | | Add 'max-frequency' for sdhci node for clock init. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | rockchip: Fix veyron-minnie's Kconfig descriptionMartin Michlmayr2017-01-11-1/+1
| | | | | | | | | | | | | | | | | | | | | The veyron-minnie Kconfig referred to jerry by mistake. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: dts: popmetal: add usb host power supply nodeKever Yang2017-01-11-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The popmetal board using a HOST_VBUS_DRV gpio signal to control the USB host port 5V power, add a fix regulator and pinctrl for it, and enable the USB host1 controller with the vbus-supply. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>
* | | SPL: Adjust more debug prints for ulong entry_pointTom Rini2017-01-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | With entry_point now being an unsigned long we need to adapt the last two debug prints to use %lX not %X. Fixes: 11e1479b9e67 ("SPL: make struct spl_image 64-bit safe") Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge tag 'xilinx-for-v2017.03' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-01-11-7/+138
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2017.03 - ATF handoff - DT syncups - gem: Use wait_for_bit(), add simple clk support - Simple clk driver for ZynqMP - Other small changes
| * | | ARM64: zynqmp: Generate handoff structure for ATFMichal Simek2017-01-10-1/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx ATF extending options for passing images from BL2(FSBL) to BL31. U-Boot SPL is FSBL replacement that's why it should generate handoff structure the same. Support only one entry which is U-Boot in EL2 itself. When FIT image is adopted structure generate should be data driven. Currently ATF is placing this structure at the beggining of OCM which is rewriting early parts of ATF which should be unused at that time. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynqmp: Make SYS_VENDOR configurableMike Looijmans2017-01-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Fix i2c node's compatible stringMoritz Fischer2017-01-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: zynq_gem: Use clock driver for ZynqMPSiva Durga Prasad Paladugu2017-01-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable and use the clock driver routine defined in clock driver toset required clock appropriately. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add idle state for ZynqMPStefan Krsmanovic2017-01-10-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the idle-states node to describe zynqmp idle states. Only cpu-sleep-0 idle state is added in this patch. References to the idle-states node are added in all CPU nodes. Time values: entry/exit latencies and min-residency, needs to be tuned. arm,psci-suspend-param is selected to comply with PSCIv1.0 and Extended StateID format. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Fix usb nodes for dc1 and dc2Michal Simek2017-01-10-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix DT binding for usb nodes. Setup correct aliases and enable dwc3 nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add missing earlycon for ep108Michal Simek2017-01-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Just sync between version. Others zynqmp boards have this setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | ARM64: zynqmp: clk: Add the clock for watchdogShubhrajyoti Datta2017-01-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The watchdog clock node is missing. Add the same. This solves the below error. cdns-wdt fd4d0000.watchdog: input clock not found cdns-wdt: probe of fd4d0000.watchdog failed with error -2 Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source propertySudeep Holla2017-01-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Though the keyboard driver for GPIO buttons(gpio-keys) will continue to check for/support the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source, "wakeup-source" is the new standard binding. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property in order to avoid any futher copy-paste duplication. Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Remove spi-max-frequencyMichal Simek2017-01-10-2/+0
| | |/ | |/| | | | | | | | | | | | | | | | spi-max-frequency for spi bus depends on devices which are connected to it. Remove this parameter from dtsi file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | mmc: move more driver config options to KconfigMasahiro Yamada2017-01-11-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move (and rename) the following CONFIG options to Kconfig: CONFIG_DAVINCI_MMC (renamed to CONFIG_MMC_DAVINCI) CONFIG_OMAP_HSMMC (renamed to CONFIG_MMC_OMAP_HS) CONFIG_MXC_MMC (renamed to CONFIG_MMC_MXC) CONFIG_MXS_MMC (renamed to CONFIG_MMC_MXS) CONFIG_TEGRA_MMC (renamed to CONFIG_MMC_SDHCI_TEGRA) CONFIG_SUNXI_MMC (renamed to CONFIG_MMC_SUNXI) They are the same option names as used in Linux. This commit was created as follows: [1] Rename the options with the following command: find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \ -type f -print | xargs sed -i -e ' s/CONFIG_DAVINCI_MMC/CONFIG_MMC_DAVINCI/g s/CONFIG_OMAP_HSMMC/CONFIG_MMC_OMAP_HS/g s/CONFIG_MXC_MMC/CONFIG_MMC_MXC/g s/CONFIG_MXS_MMC/CONFIG_MMC_MXS/g s/CONFIG_TEGRA_MMC/CONFIG_MMC_SDHCI_TEGRA/g s/CONFIG_SUNXI_MMC/CONFIG_MMC_SUNXI/g ' [2] Commit the changes [3] Create entries in driver/mmc/Kconfig. (copied from Linux) [4] Move the options with the following command tools/moveconfig.py -y -r HEAD \ MMC_DAVINCI MMC_OMAP_HS MMC_MXC MMC_MXS MMC_SDHCI_TEGRA MMC_SUNXI [5] Sort and align drivers/mmc/Makefile for readability Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2017-01-10-0/+8
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| * | | am33xx: board: init usb ether gadget for rndis supportMugunthan V N2017-01-09-0/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | Add usb ether gadget device with usb_ether_init() when CONFIG_DM_ETH and CONFIG_USB_ETHER are defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-01-10-172/+473
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| * | sunxi: A64: enable SPLAndre Przywara2017-01-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the SPL is ready to be compiled in AArch64 and the DRAM init code is ready, enable SPL support for the A64 SoC and in the Pine64 defconfig. For now we keep the boot0 header in the U-Boot proper, as this allows to still use boot0 as an SPL replacement without hurting the SPL use case. We disable FEL support for now by making its compilation conditional and disabling it for ARM64, as the code isn't ready yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: DRAM: fix H3 DRAM size display on aarch64Andre Przywara2017-01-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the output of the DRAM size on AArch64 SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: H3/A64: fix non-ODT settingAndre Przywara2017-01-04-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this. Reported-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: A64: use H3 DRAM initialization code for A64 as wellJens Kuske2017-01-04-56/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A64 DRAM controller is very similar to the H3 one, so the code can be reused with some small changes. This refactoring does not change the code size for the existing H3 part. [Andre: rework from #ifdefs to using socid parameters in static functions, minor fixes, merging in fixes from Jens] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: clocks: Use the correct pattern register for PLL11Philipp Tomsich2017-01-04-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: H3: add DRAM controller single bit delay supportJens Kuske2017-01-04-27/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as well) only applied coarse delay line settings, with one delay value for all the data lines in each byte lane and one value for the control lines. Instead of setting the delays for whole bytes only allow setting it for each individual bit. Also add support for address/command lane delays. For the purpose of this patch the rules for the existing coarse settings were just applied to the new scheme, so the actual register writes don't change for the H3. Other SoCs will utilize this feature later properly. With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from 2296 to 2344 Bytes. [Andre: move delay parameters into macros to ease later sharing, use defines for numbers of delay registers, extend commit message] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: H3: add and rename some DRAM contoller registersJens Kuske2017-01-04-36/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | The IOCR registers got renamed to BDLR to match the public documentation of similar controllers. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: H3: Rework MBUS priority setupPhilipp Tomsich2017-01-04-24/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the MBUS priority setup was done by writing "magic" values taken from a DRAM controller register dump after a boot0 run. By peeking at the Linux (sic!) MBUS driver [1] from the Allwinner BSP kernel, we learned more about the actual meaning of those bits. Add macros and refactor the setup function to make the MBUS setup much more readable and meaningful. The actual values used now are a transformation of the values used before, which are assembled by the new code to result in the same register writes. So this rework does not change any settings, also the code size stays the same. The respective source files in the BSP kernel had a proper GPL header, so lifting this code and information into U-Boot is legal. [Andre: provide a convenience macro to fit definitions on one line] [1] https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65/drivers/bus/sunxi_mbus.c Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: A64: do an RMR switch if started in AArch32 modeAndre Przywara2017-01-04-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC starts execution in AArch32 mode, and both the boot ROM and Allwinner's boot0 keep running in this mode. So U-Boot gets entered in 32-bit, although we want it to run in AArch64. By using a "magic" instruction, which happens to be an almost-NOP in AArch64 and a branch in AArch32, we differentiate between being entered in 64-bit or 32-bit mode. If in 64-bit mode, we proceed with the branch to reset, but in 32-bit mode we trigger an RMR write to bring the core into AArch64/EL3 and re-enter U-Boot at CONFIG_SYS_TEXT_BASE. This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode, so we can use the same start code for the SPL and the U-Boot proper. We use the existing custom header (boot0.h) functionality, but restrict the existing boot0 header reservation to the non-SPL build now. A SPL wouldn't need such header anyway. This allows to have both options defined and lets us use one for the SPL and the other for U-Boot proper. Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original ARM assembly code and instructions how to re-generate the encoded version. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
generated by cgit v1.1 at 2024-11-18 14:40:34 +0000