summaryrefslogtreecommitdiff
path: root/arch/arm
Commit message (Collapse)AuthorAgeLines
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-24-3/+113
|\
| * armv7: ls102xa: Move smmu and stream id initialization into the common soc codeAlison Wang2016-02-24-0/+50
| | | | | | | | | | | | | | | | The initialization for smmu and stream id is moved into the common soc code. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-layerscape: fdt: add fixup for Fman ucodeQianyu Gong2016-02-24-0/+7
| | | | | | | | | | | | | | Add fdt fixup to insert Fman firmware into the device tree. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: Implement workaround for erratum A009660Mingkai Hu2016-02-24-0/+20
| | | | | | | | | | | | | | | | | | Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: enable workaround for errarum A009942Shengzhou Liu2016-02-24-0/+1
| | | | | | | | | | | | | | DDR erratum A-009942 applies to LS1043A. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1021aqds: Enable driver model lpuart serial driverYork Sun2016-02-24-0/+17
| | | | | | | | | | | | | | | | | | | | | | Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart to driver model suport. Enable lpuart port driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
| * arm: ls1021aqds: Convert to driver model and enable serial supportYork Sun2016-02-23-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Split duart configuration as device tree file. Move /chosen node out of board commone device tree. Convert ls1021aqds nor and SD configurations to driver model support (qspi already uses DM). Enable ns16550 DM serial driver for nor configurations. Signed-off-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
* | rpi: set board serial number in environmentLubomir Rintel2016-02-24-0/+11
| | | | | | | | | | | | | | | | | | Gets propagated into the device tree and then into /proc/cpuinfo where users often expect it. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
* | stm32: add support for stm32f7 & stm32f746 discovery boardVikas Manocha2016-02-24-0/+535
| | | | | | | | | | | | This patch adds support for stm32f7 family & stm32f746 board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | gpio: stm32_gpio: move base addresses to the soc fileVikas Manocha2016-02-24-0/+18
| | | | | | | | | | | | | | Base addresses for GPIOs could be different for different socs, this patch moves the base addresses from driver to the soc specific location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | gpio: stm32_gpio: move clock config from driver to boardVikas Manocha2016-02-24-0/+59
| | | | | | | | | | | | | | This patch removes the gpio clock enable from gpio driver & move it in the board code, making it possible to use the gpio driver with other socs. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-02-23-7/+58
|\ \
| * | sunxi: H3: Add support for the host usb-physJelle van der Waa2016-02-23-7/+58
| |/ | | | | | | | | | | | | | | Add support for phy 1-3. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: zynq: Add reset-gpio property for USB on ZyboMichal Simek2016-02-22-1/+2
| | | | | | | | | | | | | | | | DTS syncup with Linux kernel. Add missing reset-gpio property. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Enable u-boot,dm-pre-reloc for qspiNathan Rossi2016-02-22-0/+3
| | | | | | | | | | | | | | | | | | | | Enable u-boot,dm-pre-reloc for qspi for zc706, zed and microzed. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Remove unused SPI base addressesMichal Simek2016-02-22-5/+0
|/ | | | | | | | Remove unused macros. Adresses are taken from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-02-21-3/+938
|\
| * imx: mx7d: isolate resources to domain 0 for A7 corePeng Fan2016-02-21-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals affected by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is to set the peripherals to Domain0 by A core, since A core in Domain0. The peripherals which will be used by M4, will be set to Domain1 by M4. For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will set WDOG4 to domain1, because M4 will use WDOG4. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1. This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7: implement functions to boot auxiliary corePeng Fan2016-02-21-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: implement functions to boot auxiliary corePeng Fan2016-02-21-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx-common: introduce boot auxiliary corePeng Fan2016-02-21-0/+79
| | | | | | | | | | | | | | | | | | | | | | To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by auxiliary core, "bootaux 0x70000000". Introduce Kconfig option IMX_BOOTAUX. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7d: clock support for RDCPeng Fan2016-02-21-0/+6
| | | | | | | | | | | | If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7d: Add RDC supportPeng Fan2016-02-21-0/+182
| | | | | | | | | | | | | | | | Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6sx Add RDC mappings of masters and peripheralsPeng Fan2016-02-21-0/+159
| | | | | | | | | | | | | | Add the definitions for the RDC mappings for i.MX6 SoloX. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx-common: introduce Resource Domain Controller supportPeng Fan2016-02-21-0/+304
| | | | | | | | | | | | | | | | | | Introduce Resource Domain Controller support for i.MX. Now i.MX6SX and i.MX7D supports this feature to assign masters and peripherals to different domains. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: introduce rdc regsPeng Fan2016-02-21-0/+24
| | | | | | | | | | | | | | | | Introudce rdc regs structure and rdc sema reg structure for i.MX6. For now, to i.MX6, only i.MX6SX supports this. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: Implement mmc_get_env_partSoeren Moch2016-02-21-3/+33
| | | | | | | | | | | | | | | | | | | | commit 216d286c7e3d3d83d4d8ccaf0415192e1b1040c0 [imx: mx6: implement mmc_get_env_dev] introduced selection of the environment device according to the boot device when booting from SD/MMC. Extend this functionality for also selecting the device partition. Signed-off-by: Soeren Moch <smoch@web.de>
| * imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7Ulises Cardenas2016-02-21-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-20-254/+307
|\ \
| * | ARM: Add Support for the VInCo platformGregory CLEMENT2016-02-19-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versatile Industrial Communication platform is a community oriented board from Landis + Gyr. It comes with: - an RS-485 port - 2 Ethernet ports - a wireless M-BUS - a 4G modem - a 4MB SPI flash - a 4GB eMMC Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> [rebase on current TOT] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: sama5d2: configure the L2 cache memorySamuel Mescoff2016-02-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: at91: Add support for DENX MA5D4 SoM and EVKMarek Vasut2016-02-18-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI CAN controllers and DRAM, the baseboard contains UART connectors, ethernet port, microSD slot, LCD header, 2x CAN connector and a lot of expansion headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clean up the PMC_PLLICPR init codeWenyou Yang2016-02-18-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the PMC_PLLICPR init function, use this function to clean up the code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clock: add PMC_PLLICPR init functionWenyou Yang2016-02-18-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | To avoid the duplicated code, add the PMC_PLLICPR init function. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clock: add PLLB enable/disable functionsWenyou Yang2016-02-18-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid the duplicated code, add the PLLB handle functions. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de> [add enable/disable functions to arm920t] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: armv7: clean up UTMI PLL handle codeWenyou Yang2016-02-18-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the UTMI PLL enable function, use this function to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clock: add UTMI PLL enable/disable functionWenyou Yang2016-02-18-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid the duplicated code, add the UTMI PLL handle functions, and add PMC_USB init function too. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: cpu: at91: clean up peripheral clock codeWenyou Yang2016-02-18-203/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the new peripheral clock handle functions, use these functions to clean up the duplicated code. Meanwhile, remove unneeded header file include, at91_pmc.h. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixup for arm920t code] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clock: add a new file to handle clockWenyou Yang2016-02-18-33/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reduce the duplicated code, add a new file to accommodate the peripheral's and system's clock handle code, shared with the SoCs with different ARM core. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: asm/at91_pmc.h: fix trival register offsetWenyou Yang2016-02-18-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary #ifdef CPU_HAS_PCR. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: tegra: enable USB device mode port on DalmoreStephen Warren2016-02-18-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows U-Boot to expose UMS and DFU protocols on this port in device mode, or to act as a USB host on the port, using an "OTG" (micro-B to female A host) cable. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | video: tegra: Correct a Kconfig warning with VIDCONSOLE_AS_LCDSimon Glass2016-02-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new feature causes a Kconfig warning on boards without a display enabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: video: Clean up the old LCD/PWM driver codeSimon Glass2016-02-16-147/+2
| | | | | | | | | | | | | | | | | | | | | | | | Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we are using driver model for video. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: video: Move LCD driver to use the DM PWM driverSimon Glass2016-02-16-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | Use the driver-model PWM driver in preference to the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: video: Move LCD enums into the driverSimon Glass2016-02-16-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to have these in a separate file as they are not referenced from anywhere else. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: video: Convert tegra20 LCD driver to driver modelSimon Glass2016-02-16-26/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this driver over to use driver model. This involves rearranging the code somewhat. The effect is that everything is run from the probe() method. Boards which use this are fixed up, but only seaboard is tested. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: video: Merge the two config structures togetherSimon Glass2016-02-16-39/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We have a structure for the display panel and another for the controller. There is some overlap between them. Merge them to simplify the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: video: Merge the display driver into one fileSimon Glass2016-02-16-401/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we have code in arch/arm and code in drivers/video. Move it all into drivers/video since it is a display driver and our current approach is to put all driver code in drivers/. Make a few functions static now that they are not used outside the file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: dts: Sync tegra20.dtsi with Linux v4.4Simon Glass2016-02-16-271/+560
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file has changed quite a bit since it was set up. Sync it back with Linux v4.4. Adjust the users slightly to cope with the changes: - the host1x node is now called host1x@50000000 - we need a clocks node to provide the clk32k_in phandle - active usb nodes need status = "okay" - active i2c nodes need status = "okay" Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | tegra: video: Rename CONFIG_VIDEO_TEGRA to CONFIG_VIDEO_TEGRA20Simon Glass2016-02-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option refers only to the tegra20 video driver, so name it as such to avoid confusion with tegra124. Also move this option to Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-26 04:48:00 +0000