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* imx: mx6sll: add clock supportPeng Fan2016-12-16-7/+21
| | | | | | | Add clock support for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: clock: gate clk before changing pix clk muxPeng Fan2016-12-16-21/+31
| | | | | | | | | | | The LCDIF Pixel clock mux is not glitchless, so need to gate before changing mux. Also change enable_lcdif_clock prototype with a new input parameter to indicate disable or enable. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sl: add lcdif clock supportPeng Fan2016-12-16-19/+80
| | | | | | Add lcdif clock support for i.MX6SL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: mx6: lcdif: gate clock before changing muxPeng Fan2016-12-16-0/+10
| | | | | | | | The mux for the lcd clock is not glitchless, so need to first gate the clock before changing the mux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: fix mmdc ch0 clk for 6SLPeng Fan2016-12-16-0/+5
| | | | | | | | | | >From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sll: add iomux settingsPeng Fan2016-12-16-5/+11
| | | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx-common: timer: add i.MX6SLL supportPeng Fan2016-12-16-3/+7
| | | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sll: update register addressPeng Fan2016-12-16-27/+50
| | | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6sll: add pinmux header filesPeng Fan2016-12-16-0/+1021
| | | | | | | Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: add i.MX 6SLL CPU typePeng Fan2016-12-16-1/+5
| | | | | | | | Add i.MX6SLL cpu type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* board/liteboard: Add support for liteBoardMarcin Niestroj2016-12-16-0/+5
| | | | | | | | | | | | liteBoard is a development board which uses liteSOM as its base. Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
* ARM: imx6ul: Add support for liteSOMMarcin Niestroj2016-12-16-0/+231
| | | | | | | | | | | | | | | | liteSOM is a System On Module (http://grinn-global.com/litesom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * NXP i.MX6UL processor * 256M or 512M DDR3 memory * optional eMMC (uSDHC2) Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-* directory and make it possible to reuse initialization code (i.e. DDR, eMMC init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
* udoo_neo: Add thermal supportBreno Lima2016-12-16-0/+2
| | | | | | | Add thermal support on the Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* udoo_neo: Move MX6SX configuration to KconfigBreno Lima2016-12-16-0/+1
| | | | | | | | | It's not necessary to define the processor in the defconfig file. The preferred method to select the SoC is via Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* arm: imx: initial support for colibri imx6Max Krummenacher2016-12-16-0/+8
| | | | | | | | This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
* arm: imx: initial support for apalis imx6Max Krummenacher2016-12-16-0/+8
| | | | | | | | This adds board support for the Toradex module family Apalis iMX6. The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
* ARM: dts: vf: Fix warning about missing reg propertyStefan Agner2016-12-16-0/+2
| | | | | | | | | Add proper reg values for the two AIPS bus nodes. This avoids this two warnings: Node /soc/aips-bus@40000000 has a unit name, but no reg property Node /soc/aips-bus@40080000 has a unit name, but no reg property Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-12-16-1938/+3806
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| * Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-12-64/+261
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| | * arm64: mvebu: Add L3 cache flush functionality to A8K familyKonstantin Porotchkin2016-12-12-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Add pin control nodes to A8K family DTS filesKonstantin Porotchkin2016-12-12-0/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pin control nodes to APN806, CP-master, CP-slave and Armada-7040 and Armada-8040 boards DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-12-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| | * arm64: mvebu: Modify the A8K SPI and I2C config in DTSKonstantin Porotchkin2016-12-12-67/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the Armada-8040-db and Armada-7040-db SPI and I2C DTS settings with latest DB settings: - 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO) - 8040-db: disable cps_i2c0 on CP1 - 8040-db: enable spi1 on CP1 (the new location of the boot flash) The spi1 on CP1 is aliased as spi0 since this is the way the driver enumerates it. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-12-12-1857/+2691
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| | * | ARM: uniphier: remove BLK selectMasahiro Yamada2016-12-11-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a user configurable option, but "select BLK" forces users to enable it. Even with this commit, BLK is still enabled by "default y if DM_MMC" for UniPhier SoCs; the difference is users can disable it if they do not need it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: dts: uniphier: sync Device Tree with LinuxMasahiro Yamada2016-12-11-1851/+2684
| | | | | | | | | | | | | | | | | | | | | | | | Sync with the latest kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: remove unneeded parenthesesMasahiro Yamada2016-12-10-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Just a cosmetic cleanup. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: remove unneeded initializerMasahiro Yamada2016-12-10-2/+4
| | |/ | | | | | | | | | | | | | | | This will be used to store the return value of readl(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evmJyri Sarha2016-12-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | spl: uniphier: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-5/+0
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: sunxi: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-9/+0
| | | | | | | | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | spl: Add a name to the SPL load-image methodsSimon Glass2016-12-09-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | arm: armv7: add us timer for bootstagePatrick Delaunay2016-12-09-1/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | solve issue when bootstage is used with armV7 generic timer first call of timer_get_boot_us() use the function get_timer() before timer initialization (arch.timer_rate_hz = 0) => div by 0 Commit-notes When I activate bootstage on ARMV7 architecture with platform using the generic armv7 timer defined in file ./arch/arm/cpu/armv7m/timer.c I have a issue because gd->arch.timer_rate_hz = 0 For me the get_timer() function should not used before timer_init (which initialize gd->arch.timer_rate_hz) at least for the ARMV7 timer. But in the init sequence, the first bootstage fucntion is called before timer_init and this function use the timer function. For me it is a error in the generic init sequence : mark_bootstage is called before timer_init. static init_fnc_t init_sequence_f[] = { .... arch_cpu_init_dm, mark_bootstage, /* need timer, go after init dm */ ... #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \ defined(CONFIG_SPARC) timer_init, /* initialize timer */ #endif ....... To solve the issue for all the paltform, we can move timer_init() call just before mark_bootstage() in this array... It should be ok for ARMV7 but I don't sure for other platform impacted - the other ARM platform or ARMV7 wich don't use generic timer - MIPS BLACKFIN NDS32 or SPARC and I don't sure of impact for other function called (board_early_init_f for example....) => This patch solve issue only in timer armv7 get_boot_us() can be called everytime without div by 0 issue (gd->arch.timer_rate_hz is not used) END Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
| * Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"Tom Rini2016-12-09-0/+2
| | | | | | | | | | This reverts commit 3edc0c252257e4afed163a3a74aba24a5509b198, reversing changes made to bb135a0180c31fbd7456021fb9700b49bba7f533.
| * Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-12-09-2/+0
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| | * block: Move ceva driver to DMMichal Simek2016-12-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Series-to: sjg, agraf@suse.de Series-cc: uboot Series-version: 4 Series-changes: 2 - make ceva_init_sata static - Move SATA_CEVA to defconfig - Initalized max_lun and max_id platdata Series-changes: 3 - Extend Kconfig help description - sort dm.h - Remove SPL undefinition from board file - Fix Kconfig dependecies
| * | qts-filter.sh: strip DOS line endings and handle continuation linesBill Randle2016-12-06-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some Altera Quartus generated files have long lines that are split with a '\' at the end of the line. It also wOn Windows, rites files in DOS format, which can confuse some of the processing scripts in this file. This patch solves both issues. Signed-off-by: Bill Randle <bill.randle@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * | ARM: socfpga: Add boot0 hook to prevent SPL corruptionMarek Vasut2016-12-06-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | socfpga: add support for Terasic DE1-SoC boardAnatolij Gustschin2016-12-06-0/+74
| |/ | | | | | | | | | | | | | | Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
| * Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-12-05-1/+59
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| | * armv8: QSPI: Add AHB bus 16MB+ size supportYuan Yao2016-12-05-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * ls1021a: QSPI: update the node for QSPI supportYuan Yao2016-12-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the name for register space and memory space. <0x1550000 0x10000 > is the QSPI register space. <0x40000000 0x4000000> is the QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * armv8: ls2080a: Add serdes1 protocol 0x3b supportPriyanka Jain2016-12-05-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu2016-12-05-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
| * | Merge git://www.denx.de/git/u-boot-i2cTom Rini2016-12-05-0/+2
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| | * arm: samsung: Convert s5p_goni and smdkc100 to DM_I2CSimon Glass2016-12-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | These are the last two samsung boards that don't use DM_I2C. Move them over, leaving #ifdefs to allow the maintainer to complete this work. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| | * arm: exynos: i2c: Convert exynos boards to use DM_I2CSimon Glass2016-12-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three boards are still not converting to use DM_I2C. They are also using the old PMIC framework. Rather than removing them, add #ifdefs to allow them to continue to build. This will give the maintainers a little more time to decide whether to convert them or not. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * | arm64: mvebu: Restrict memory size to a usable maximumStefan Roese2016-12-05-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all memory is mapped in the MMU. So we need to restrict the memory size so that U-Boot does not try to access it. Also, the internal registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB are mapped for system memory. This is what we pass to the U-Boot subsystem here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
| * | arm64: mvebu: Add regions for PCI spaces to the memory mapStefan Roese2016-12-05-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To use the PCIe driver, its controller memory and the PCIe regions need to get mapped in the MMU. Otherwise these areas can't be accessed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
| * | arm64: mvebu: Init COMPHY from the slave-CP on the A8kStefan Roese2016-12-05-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada8k implements 2 CPs (communication processors) and the 2nd CP also is equipped with a COMPHY controller. This patch now loops over all enabled MISC devices (CP110) enabled in the DT to initialize all CPs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
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