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* rockchip: rk3399: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-0/+40
| | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3036: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-0/+41
| | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* Merge branch 'sun9i-a80-spl' of http://git.denx.de/u-boot-sunxiTom Rini2016-10-30-20/+1666
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| * sunxi: Add support for SID e-fuses on sun9iChen-Yu Tsai2016-10-30-0/+2
| | | | | | | | | | | | | | | | | | The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses are at an offset of 0x200 within the SID address space. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: add initial clock setup for sun9i for SPLPhilipp Tomsich2016-10-30-5/+223
| | | | | | | | | | | | | | | | | | | | This is a cleaned up version set_pll() from Allwinner's boot0 source (bootloader/basic_loader/bsp/bsp_for_a80/common/common.c). [wens@csie.org: Added commit message; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable SMP mode for the boot CPU on sun9i (A80)Philipp Tomsich2016-10-30-1/+2
| | | | | | | | | | | | | | | | | | | | Since the A80 has many cores which we intend to use in SMP fashion, we should set the SMP bit for the boot CPU. [wens@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: add gtbus-initialisation for sun9iPhilipp Tomsich2016-10-30-1/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: DRAM initialisation for sun9iPhilipp Tomsich2016-10-30-13/+1269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-10-30-4/+47
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| * sunxi: A64: enable USB supportAmit Singh Tomar2016-10-30-3/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dts: Pine64: add Ethernet aliasAndre Przywara2016-10-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | The sun8i-emac driver works fine with the A64 Ethernet IP, but we are missing an alias entry to trigger the driver instantiation by U-Boot. Add the line to point U-Boot to the Ethernet DT node. This enables TFTP boot on the Pine64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXIJagan Teki2016-10-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SUNXI -> CONFIG_ARCH_SUNXI and removed CONFIG_SUNIX from config_whitelist.txt Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-10-29-2/+15
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| * | ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-27-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | ARM: uniphier: update DRAM init code for LD11 SoCMasahiro Yamada2016-10-29-23/+391
| | | | | | | | | | | | | | | | | | Introduce run-time DDR PHY training. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: support DDR PHY parameter dump command for LD11Masahiro Yamada2016-10-29-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: refactor DDR PHY parameter dump commandMasahiro Yamada2016-10-29-44/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoCMasahiro Yamada2016-10-29-294/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3Masahiro Yamada2016-10-29-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The USB boot without the stand-by MPU is available on ES3 or later of LD11 SoC, but the code in this if-conditional block must not be run when booting from USB. Check if the boot device is USB, and skip the code in the case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabledMasahiro Yamada2016-10-29-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8Masahiro Yamada2016-10-29-3/+3
| | | | | | | | | | | | | | | | | | The status register should be polled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.hMasahiro Yamada2016-10-29-4/+4
| | | | | | | | | | | | | | | | | | | | | This PHY might be used for other SoCs in the future. Avoid including the SoC name in the header name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: update DRAM init code for LD20 SoC (3rd)Masahiro Yamada2016-10-29-36/+83
| | | | | | | | | | | | | | | | | | | | | | | | - Constify UMC setting data arrays - Merge data arrays *_d0 and *_d1. - Add PHY parameters for LD20 C1 board Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: remove unused board attribute macrosMasahiro Yamada2016-10-29-3/+0
| | | | | | | | | | | | | | | | | | After SoC evaluation, they turned out unnecessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: enable SSC for more PLLs for LD20 SoCMasahiro Yamada2016-10-29-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: remove unneeded mdelay() in PLL setting functionMasahiro Yamada2016-10-29-2/+0
| | | | | | | | | | | | | | | | | | This delay is already cared by the callers of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: adjust fdt_file environment handling to latest LinuxMasahiro Yamada2016-10-29-12/+9
| |/ |/| | | | | | | | | | | The environment fdt_file is useful to remember the appropriate DTB file name. Adjust it to the recent renaming in the upstream kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-10-28-70/+109
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| * | ARM: at91/dt: sama5d2: Fix the warning from dtcWenyou Yang2016-10-28-70/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the warning from dtc like, ---8<---- Warning (unit_address_vs_reg): Node /ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but no unit name --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | arm, at91: add icache supportHeiko Schocher2016-10-28-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add at least icache support for at91 based boards. This speeds up NOR flash access on an at91sam9g15 based board from 15.2 seconds reading 8 MiB from a SPI NOR flash to 5.7 seconds. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | ARM: at91: clock: correct PRES offset for at91sam9x5Heiko Schocher2016-10-28-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | on at91sam9x5 PRES offset is 4 in the PMC master clock register. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Andreas Bießmann <andreas@biessmann.org>
| * | arm: at91: mpddrc: add missing MPDDRC_MD definesHeiko Schocher2016-10-28-0/+3
| |/ | | | | | | | | | | | | | | add missing MPDDRC_MD defines Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-28-7/+4505
|\ \ | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
| * | arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/DualJagan Teki2016-10-26-1/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.CoreM6 Quad/Dual modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DQ, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: dts: imx6q: Add pinctrl definesJagan Teki2016-10-26-0/+1047
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add imx6q pinctrl defines support from Linux. Here is the last commit: "ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ" (sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: dts: Add devicetree for i.MX6QJagan Teki2016-10-26-0/+300
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6Q dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | engicam: icorem6: Add DM_GPIO, DM_MMC supportJagan Teki2016-10-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DM_GPIO, DM_MMC support for u-boot and disable for SPL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/SoloJagan Teki2016-10-26-1/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.CoreM6 DualLite/Solo modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DL, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: dts: imx6dl: Add pinctrl definesJagan Teki2016-10-26-0/+1091
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add imx6dl pinctrl defines support from Linux. Here is the last commit: "ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ" (sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: dts: Add devicetree for i.MX6DQLJagan Teki2016-10-26-0/+1281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6DQL dtsi support from Linux. Here is the last commit: "ARM: dts: imx6qdl: Fix SPDIF regression" (sha1: f065e9e4addd75c21bb976bb2558648bf4f61de6) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: dts: Add devicetree for i.MX6DLJagan Teki2016-10-26-0/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6DL dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial supportJagan Teki2016-10-26-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Log for i.CoreM6 DualLite/Solo Starter Kit: ----------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 31C Reset cause: POR DRAM: 256 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device switch to partitions #0, OK mmc0 is current device reading boot.scr ** Unable to read file boot.scr ** reading zImage 6741808 bytes read in 341 ms (18.9 MiB/s) Booting from mmc ... reading imx6dl-icore.dtb 30600 bytes read in 19 ms (1.5 MiB/s) Booting using the fdt blob at 0x18000000 Using Device Tree in place at 18000000, end 1800a787 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 Boot Log for i.CoreM6 Quad/Dual Starter Kit: -------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6Q rev1.2 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Reset cause: POR DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | imx-common: compile plugin codePeng Fan2016-10-24-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_USE_IMXIMG_PLUGIN is selected, plugin.bin will be generated under board/$(BOARDDIR)/. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | imx-common: introduce USE_IMXIMG_PLUGIN KconfigPeng Fan2016-10-24-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Introduce USE_IMXIMG_PLUGIN Kconfig Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | imx: mx7: Add plugin supportPeng Fan2016-10-24-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mx7_plugin.S which calls boot rom setup function, generate the second ivt, and jump back to boot rom. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | imx: mx6: Add plugin supportPeng Fan2016-10-24-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mx6_plugin.S which calls boot rom setup function, generate the second ivt, and jump back to boot rom. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
| * | arm: imx-common: introduce back usec2ticksPeng Fan2016-10-17-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit "2bb014820c49a63902103bac710bc86b5772e843" do some clean up to use the code in lib/time.c. But usec2ticks is still being used by security related job ring code. Bring back the function to avoid build break when CONFIG_FSL_CAAM is defined. The computation logic has been changed, using 64-bit variable to ease the process, making it work on older (MX5) platforms. Signed-off-by: Peng Fan <van.freenix@gmail.com> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
| * | arm: imx-common: add SECURE_BOOT option to KconfigGary Bisson2016-10-17-0/+7
| | | | | | | | | | | | | | | | | | So the option can easily be selected through menuconfig. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
* | | drivers/pci/Kconfig: Add PCITom Rini2016-10-27-2/+0
| |/ |/| | | | | | | | | | | Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | Fix codying style broken by recent libfdt syncMasahiro Yamada2016-10-24-1/+1
| | | | | | | | | | | | | | | | | | Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-06 03:19:14 +0000