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* ARM: bcm283x: Switch to generic timerMarek Vasut2015-05-28-59/+1
| | | | | | | | | | | Switch to generic timer implementation from lib/time.c . This also fixes a signed overflow which was in __udelay() implementation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tyler Baker <tyler.baker@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: bcm283x: Reorder timer.hMarek Vasut2015-05-28-5/+10
| | | | | | | | Reorder the timer.h file so it can be included from board config file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tyler Baker <tyler.baker@linaro.org>
* ARM: bcm283x: Repair wdog.hMarek Vasut2015-05-28-2/+2
| | | | | | | | Trivially fix the include check in wdog.h. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tyler Baker <tyler.baker@linaro.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-05-26-46/+202
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| * arm, imx6: add support for aristainetos2 boardHeiko Schocher2015-05-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for imx6dl based aristainetos2 board U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27) CPU: Freescale i.MX6DL rev1.1 at 792 MHz Reset cause: WDOG Board: aristaitenos2 Watchdog enabled I2C: ready DRAM: 1 GiB NAND: 1024 MiB MMC: FSL_SDHC: 0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lg4573 (480x800) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => Signed-off-by: Heiko Schocher <hs@denx.de>
| * i2c, mxc: rework i2c base address names for different SoCsHeiko Schocher2015-05-26-7/+7
| | | | | | | | | | | | | | rework and unify i2c address names for different SoCs, which use the mxc_i2c driver. Signed-off-by: Heiko Schocher <hs@denx.de>
| * arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-26-12/+29
| | | | | | | | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| * imx: dma: correct MXS_DMA_ALIGNMENTPeng Fan2015-05-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * wandboard: Switch to SPL supportFabio Estevam2015-05-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we need to build one U-boot image for each of the wandboard variants: quad, dual-lite and solo. By switching to SPL we can support all these variants with a single binary, which is very convenient. Based on the work from Richard Hu. Tested kernel booting on the three boards. Signed-off-by: Richard Hu <hakahu@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6: add display of CPU temperature grade in print_cpuinfo()Tim Harvey2015-05-19-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info along with the current temperature. Before: CPU: Temperature 42 C After: CPU: Automotive temperature grade (-40C to 125C) at 42C CPU: Industrial temperature grade (-40C to 105C) at 42C CPU: Extended Commercial temperature grade (-20C to 105C) at 42C Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTPTim Harvey2015-05-19-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: display max cpu frequency in print_cpuinfo()Tim Harvey2015-05-19-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display the max CPU frequency as well as the current running CPU frequency if the max CPU frequency is available and differs from the current CPU frequency. Before: CPU: Freescale i.MX6Q rev1.2 at 792 MHz After - using an 800MHz IMX6DL (running at its max) CPU: Freescale i.MX6DL rev1.1 at 792 MHz After - using a 1GHz IMX6Q (not running at its max): CPU: Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz) Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTPTim Harvey2015-05-19-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * mx6: add OTP bank1 registersTim Harvey2015-05-19-0/+19
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specifiedTim Harvey2015-05-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support to the MMDC however enabling it on the DDR3 got missed. Make sure we enable it on the DDR3 as well. Gateworks uses Micron memory as well as Winbond in MX6. We have found in testing that we need to enable fast-exit for Winbond stability. Gateworks boards are currently the only boards using the MX6 SPL and enabling fast-exit mode. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm/imx-common: Fix warning 'get_reset_cause' defined but not usedPrabhakar Kushwaha2015-05-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | Fix below warning arch/arm/imx-common/cpu.c:29:14: warning: ‘get_reset_cause’ defined but not used static char *get_reset_cause(void) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6sx enable SION for i2c pin muxPeng Fan2015-05-19-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise we will get erros when doing i2c operations. error log like the following: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0xb retry=1 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | ARM: zynq: add default ps7_init_gpl.c/h for Zed, MicroZed, ZC70xMasahiro Yamada2015-05-25-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to licensing issues, the files ps7_init.c/h are not able to be distributed with U-Boot source code. Recent Xilinx tools also provide the GPL variants (ps7_init_gpl.c/h), compatible with U-Boot license. Prior to this commit, we had to copy ps7_init files into board/xilinx/zynq/ before the compile. To be more user-friendly, let's include ps7_init_gpl.c/h for Zedboard, MicroZed, ZC702, ZC706. These init code have been taken from the hwplatform_templates directory of Xilinx SDK 2014.4. You can still use customized ps7_init_gpl.c/h by enabling CONFIG_ZYNQ_CUSTOM_INIT. The recommended directory for storing them is now board/xilinx/zynq/custom_hw_platform, but board/xilinx/zynq is still supported for backward compatibility. The latter emits a warning message to prompt users to gradually switch to the new directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: add separate configuration for ZC702 and ZC706Masahiro Yamada2015-05-25-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this commit, ZC702 and ZC706 shared the same configuration and were built as follows: ZC702: make zynq_zc70x_defconfig && make ZC706: make zynq_zc70x_defconfig && make DEVICE_TREE=zynq-zc706 This commit introduces separate configuration for them, which makes the next commit much easier. Going forward, the recommended build commands are: ZC702: make zynq_zc702_defconfig && make ZC706: make zynq_zc706_defconfig && make Although the old work flow is still supported, CONFIG_TARGET_ZC70X has been marked as deprecated. If used, the warning message is shown to prompt users to switch to the new scheme. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: Use system timer implementation instead of ourMichal Simek2015-05-25-83/+1
| | | | | | | | | | | | | | Don't use error-prone arch timer code and instead use system timer implementation to simplify our code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-05-22-146/+0
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| * | arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.hYork Sun2015-05-20-146/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | ccsr_ddr structure is already defined in fsl_immap.h. Remove this duplicated define. Move fixed timing into ls1021atwr.h. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com>
* | | sunxi: video: Fix lvds panel support for sun6i+Hans de Goede2015-05-19-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | We've never tested the lvds panel support on sun6i+ SoCs until now, and unsurprisingly the lvds code needed some fixes to work on my ga10h A33 tablet with lvds panel. This makes the panel on that tablet actually work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: Make DRAM_ODT_EN Kconfig setting a boolHans de Goede2015-05-19-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of only in dram_sun4i.c and hardcoding odt_en elsewhere. Note this commit makes no functional changes for existing boards, its purpose is to allow changing the odt_en value on future A33 boards. For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs currently do) this patch turns on odt for both the DQ and the DQS lines, whereas previously it was possibly (but not desirable) to turn odt on only for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | | sunxi: Fix dram initialization not working on some a33 devicesHans de Goede2015-05-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When porting the allwinner dram init code to u-boot we missed some code setting an extra bit when doing auto dram config. This commits add this bit, fixing dram init not working on the ga10h 10" a33 tablet which I'm bringing up atm. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: add support for UART2 on A23/A33Laurent Itti2015-05-19-0/+5
|/ / | | | | | | | | | | | | | | | | | | Add support for UART2 (2-pin version but note that RTS/CTS pins are available pn that port for possible future use), can be selected in config by using CONFIG_CONS_INDEX=3 Signed-off-by: Laurent Itti <laurentitti@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-samsungTom Rini2015-05-18-28/+37
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| * exynos: clock: clean up checkpatch issuesMinkyu Kang2015-05-18-28/+37
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | arm: mx6: ddr3: Remove dead codeNikolay Dimitrov2015-05-15-22/+0
| | | | | | | | | | | | | | imx6 mmdc supports data rates up to 1066 MT/s, so remove the code handling higher data rates. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
* | mx6: Set shared override bit in PL310 AUX_CTRL registerFabio Estevam2015-05-15-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
* | hummingboard: Remove mx6solo specific supportFabio Estevam2015-05-15-5/+0
| | | | | | | | | | | | | | | | | | | | Hummingboard dual, dual-lite and solo are now supported via SPL mechanism. Remove the previous hummingboard support, which does not use SPL and supported only the solo variant. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | imx: dek_blob: Add explicit include for mapmemUlises Cardenas2015-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | Boards such as imx6q_sabresd might not have mapmem.h as part of their common library. This causes a build error if the DEK blob command is enabled. Fix: make explicit the include of mapmem.h Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com> Reviewed-by: Ruchika Gupta <Ruchika.gupta@freescale.com>
* | arm: mx6: Clamp MMDC and DDR3 clocks for timing calculationsNikolay Dimitrov2015-05-15-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed. Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
* | odroid: dts: add 'voltage-regulators' description to max77686 nodePrzemyslaw Marczak2015-05-14-0/+253
| | | | | | | | | | | | | | | | | | Adding regulators subnode to fdt max77686 node, allows properly init regulators by the max77686 regulator driver. This enables the complete functionality of the regulator command. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* | pmic: max77686 set the same compatible as in the kernelPrzemyslaw Marczak2015-05-14-4/+4
| | | | | | | | | | | | | | This commit also updates the proper dts files. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* | i2c: mxc: refactor i2c driver and support dmPeng Fan2015-05-14-8/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Introduce a new structure `struct mxc_i2c_bus`, this structure will used for non-DM and DM. 2. Remove `struct mxc_i2c_regs` structure, but use register offset to access registers based on `base` entry of `struct mxc_i2c_bus`. 3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform flags. A new flag is introduced, I2C_QUIRK_FLAG. 4. Most functions use `struct mxc_i2c_bus` as one of the parameters. Make most functions common to DM and non-DM, try to avoid duplicated code. 5. Support DM, but pinctrl is not included. Pinmux setting is still set by setup_i2c, but we do not need bus_i2c_init for DM. 6. struct i2c_parms and struct sram_data are removed. 7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist paramter of bus_i2c_init is modified to i2c index. Add new prototype i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus. Board file take the responsibility to implement this function, like this: " int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) { if (i2c_bus->index == 0) force_bus_idle(i2c_pads_info0); else if (i2c_bus->index == 1) force_bus_idle(i2c_pads_info1); else xxxxxx } " 8. Introduce a weak function, enable_i2c_clk 9. Tested on an i.MX7 platform. Log info: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver simple_bus [ ] |-- soc simple_bus [ ] | |-- aips-bus@30000000 simple_bus [ ] | | |-- anatop@30360000 simple_bus [ ] | | `-- snvs@30370000 simple_bus [ ] | |-- aips-bus@30400000 simple_bus [ ] | `-- aips-bus@30800000 i2c [ ] | |-- i2c@30a20000 i2c [ ] | `-- i2c@30a40000 simple_bus [ ] `-- regulators => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 08 50 => i2c md 8 31 0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* | imx: mx27 move GPIO_PORTx to gpio.hPeng Fan2015-05-14-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These GPIO_PORTx macros should be in gpio.h, but not in imx-regs.h. Also, imx-regs.h and iomux-v3.h has same macro defintion for GPIO_PORTx, and both of them are included in mxc_i2c.c(include mxc_i2c.h). This will incur build warnings with macro redefinition. Since iomux-v3.h is not compatible with mx27, we can not simply include iomux-v3.h for mx27, so move the GPIO_PORTx to gpio.h to fix the build warning. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | arm: Add a prototype for save_boot_params_ret()Simon Glass2015-05-14-0/+16
| | | | | | | | | | | | | | | | It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | arm: Include the .got section in the binarySimon Glass2015-05-14-1/+2
| | | | | | | | | | | | | | Commit 47ed5dd0 dropped the .got section from U-Boot binaries. This is needed for some relocations, and causes failures if missing. Add it back. Signed-off-by: Simon Glass <sjg@chromium.org>
* | tpm: Rename Infineon TPM to slb9645ttSimon Glass2015-05-14-2/+2
| | | | | | | | | | | | This name is used in Linux, so use it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sunxi: ohci: Add ohci usb host controller supportHans de Goede2015-05-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for the OHCI companion controller, which makes usb-1 devices directly plugged into to usb root port work. Note for now this switches usb-keyboard support for sunxi back from int-queue support to the old interrupt polling method. Adding int-queue support to the ohci code and switching back to int-queue support is in the works. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | arch/arm/lib/bootm-fdt.c: Guard the include of <asm/armv7.h>Tom Rini2015-05-14-0/+2
| | | | | | | | | | | | | | | | | | With d6b72da0 we started including this file unconditionally. This isn't allowed in a file that we also use on armv8. This will get cleaned up a bit better once we really start using these same features (and have similar fdt updates needed) on armv8. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-05-14-222/+1393
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| * | ARM: tegra: move NVIDIA common files to arch/arm/mach-tegraMasahiro Yamada2015-05-13-1/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the Tegra boards borrow the files from board/nvidia/common/ directory, i.e., board/nvidia/common/* are not vendor-common files, but SoC-common files. Move NVIDIA common files to arch/arm/mach-tegra/ to clean up Makefiles. As arch/arm/mach-tegra/board.c already exists, this commit renames board/nvidia/common/board.c to arch/arm/mach-tegra/board2.c, expecting they will be consolidated as a second step. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | jetson-tk1: Add PSCI configuration options and reserve secure codeIan Campbell2015-05-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The secure world code is relocated to the MB just below the top of 4G, we reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is not protected in h/w. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Boot in non-secure mode by defaultJan Kiszka2015-05-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upstream Linux is broken with default configs when PSCI, thus non-secure mode is enabled. So the user should explicitly enable this mode, e.g. when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to use). We can revert this workaround once Linux got fixed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable SMMU when going non-secureThierry Reding2015-05-13-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZone-secured requestors, hence the kernel wouldn't be able to turn the SMMU on. At the same time, enable translation for all memory clients for the same reasons. The kernel will still be able to control SMMU IOVA translation using the per-SWGROUP enable bits. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Set CNTFRQ for secondary CPUsJan Kiszka2015-05-13-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to happen for all cores. Fixing this resolves problems of KVM with emulating the generic timer/counter. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0Ian Campbell2015-05-13-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: Add PSCI support for Tegra124Jan Kiszka2015-05-13-0/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on Thierry Reding's work and uses Ian Campell's preparatory patches. It comes with full support for CPU_ON/OFF PSCI services. The algorithm used in this version for turning CPUs on and off was proposed by Peter De Schrijver and Thierry Reding in http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It consists of first enabling CPU1..3 via the PMC, just to powergate them again with the help of the Flow Controller. Once the Flow Controller is in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF PSCI requests. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-15 05:48:03 +0000