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* imx: mxs: reimplement get_cpu_revPeng Fan2015-09-02-28/+25
| | | | | | | | | | | | Rewrite get_cpu_rev, from "static const char *get_cpu_rev(void)" to "u32 get_cpu_rev(void)". To align with get_cpu_rev of other i.MXes. Also write get_imx_type to replace get_cpu_type, since we have macro named get_cpu_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx31 use new formula for get_cpu_revPeng Fan2015-09-02-1/+3
| | | | | | | | | Use new formula for get_cpu_rev, since we need to use this formula to do runtime check for all i.MXes. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx27 implement get_cpu_revPeng Fan2015-09-02-0/+6
| | | | | | | | Implement get_cpu_rev to support runtime check using is_cpu_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: add cpu type for i.MX2 and i.MX3Peng Fan2015-09-02-0/+6
| | | | | | | | Add cpu types for i.MX2/3. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6 move TARGET_xx Kconfig option to mx6 specific Kconfig filePeng Fan2015-09-02-132/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move TARGET_xx Kconfig option based on mx6 to arch/arm/cpu/armv7/mx6/Kconfig. Add enable "CONFIG_ARCH_MX6" for boards based on mx6. Then we can choose target boards using "make ARCH=arm menuconfig" with ARCH_MX6 defined. If using original way, we have no chance to enable ARCH_MX6 when "make menuconfig". Even define CONFIG_ARCH_MX6=y in xx_defconfig, kconfig will complains "arch/../configs/platinum_titanium_defconfig:3: warning: override: TARGET_PLATINUM_TITANIUM changes choice state" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Bénard <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Marek Vasut <marex@denx.de> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Soeren Moch <smoch@web.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Soeren Moch <smoch@web.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* ARM: ts4800: add ethernet supportDamien Riegel2015-09-02-0/+11
| | | | | | | | | | This commit adds ethernet support to the TS4800. Note that the MAC address is not fused on this board and have to be read from FEC PALR PAUR registers (this is how the kernel provided by Technologic Systems does it). signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: ts4800: add basic board supportLucile Quirion2015-09-02-0/+5
| | | | | | | | | | | | This commit adds basic support including: MMC, Serial console, TS4800 watchdog The config use CONFIG_SKIP_LOWLEVEL_INIT as U-boot is used as a second stage bootloader. Signed-off-by: Lucile Quirion <lucile.quirion@savoirfairelinux.com> signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Stefano Babic <sbabic@denx.de>
* arm: mxs: Fix mkimage invocationMarek Vasut2015-09-02-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove this ad-hoc mkimage invocation in MXS Makefile and replace it with the standard mkimage rule instead. This patch fixes recent build issues introduced by the patch 92a655c mkimage: Set up a file size parameter and keep it updated These build issues could be triggered by building for example the MX28EVK and the u-boot.sb image: $ make mx28evk_defconfig $ make V=1 u-boot.sb [...] make -f ./scripts/Makefile.build obj=arch/arm/cpu/arm926ejs/mxs u-boot.sb ./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage u-boot.sb ./tools/mkimage: Can't open (null): Bad address arch/arm/cpu/arm926ejs/mxs/Makefile:82: recipe for target 'u-boot.sb' failed make[1]: *** [u-boot.sb] Error 1 Makefile:989: recipe for target 'u-boot.sb' failed make: *** [u-boot.sb] Error 2 With this patch: ./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage -d arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg u-boot.sb Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Juha Lumme <juha.lumme@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* udoo: Switch to SPL supportvpeter42015-09-02-0/+1
| | | | | | | | | | | | | | | | | | | Currently we need to build one U-boot image for each of the udoo variants: quad and dual-lite. By switching to SPL we can support all two variants with a single binary. Based on the SPL for wandboard. Tested with OpenELEC (Open Embedded Linux Entertainment Center) on both boards. Signed-off-by: Peter Vicman <peter.vicman@gmail.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Peter Vicman <peter.vicman@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-31-0/+675
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| * sunxi: Enable non-secure access to RTC on sun6i (A31s)Chen-Yu Tsai2015-08-31-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On the A31s the RTC is by default secured. Thus when u-boot loads the kernel in non-secure world, the RTC is unavailable. The SoC has a TrustZone Protection Controller, which can be used to enable non-secure access to the RTC. On the A31 the TZPC doesn't seem to do anything, i.e. changes to its register contents do not affect access to the RTC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add support for the Olimex A20 EVBMarcus Cooper2015-08-31-0/+245
| | | | | | | | | | | | Signed-off-by: Marcus Cooper <codekipper@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add inet98v_rev2 defconfig and dts fileHans de Goede2015-08-31-0/+237
| | | | | | | | | | | | | | | | | | | | | | The inet98v_rev2 is a pcb used in generic A13 based tablets. It features volume buttons, a power barrel, micro-usb otg, headphone connector and a power button. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add support for gt90h-v4 tabletsHans de Goede2015-08-31-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gt90h is a pcb found in generic 9" tablets with an A23 soc, 1G RAM and 8G nand, rtl8723as usb wifi, 1 micro usb port and 1 micro sd slot. The pmic setup on this board is somewhat special, dcdc2 MUST be set to 1.1V instead of the usual 1.2V otherwise the board is very unstable. aldo1 is used to power the micro sd slot, dldo1 is used for wifi. This commit adds a defconfig + dts (as submitted to the kernel) for the gt90h-v4 pcb. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devicesSimon Glass2015-08-31-6/+23
|/ | | | | | | | | Add a TPM node to the various Chromebooks so that driver can be converted to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* ARM: dts: uniphier: add ProXstream2 and PH1-LD6b SoC/board supportMasahiro Yamada2015-08-31-2/+334
| | | | | | | | | | | | | | Initial version of DTSI for ProXstream2 and PH1-LD6b and DTS for PH1-LD6b reference board. Import from Linux with some adjustments: - Use SPDX-License-Identifier - Add clock-frequency to serial nodes - Drop unusable nodes from -ref.dts While I am here, sort Makefile entries alphabetically. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add PH1-Pro5 SoC supportMasahiro Yamada2015-08-31-0/+216
| | | | | | | | Initial version of UniPhier PH1-Pro5 device tree. (Imported from Linux with adjustment for SPDX License Identifier) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: sync with LinuxMasahiro Yamada2015-08-31-107/+472
| | | | | | | This commit imports device tree updates from Linux. It eventually adds pinctrl-related nodes and properties. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: enable SPL_OF_CONTROLMasahiro Yamada2015-08-31-61/+25
| | | | | | | | | | | | | Device Tree really improves code maintainability and is now available for SPL too. This is the state-of-the-art implementation in U-boot. The board files (platform data) are no longer needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: select SPL_DM rather than default in defconfigMasahiro Yamada2015-08-30-0/+1
| | | | | | Now UniPhier SoCs highly depend on Driver Model for SPL, too. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix build error when CONFIG_DEBUG_LL is definedMasahiro Yamada2015-08-30-0/+2
| | | | | | | The build error happens if CONFIG_DEBUG_LL and CONFIG_MACH_PH1_SLD3 are both enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: OMAP5/AM43xx: remove enabling USB clocks from enable_basic_clocks()Kishon Vijay Abraham I2015-08-28-42/+0
| | | | | | | | | | Now that we have separate function to enable USB clocks, remove enabling USB clocks from enable_basic_clocks(). Now board_usb_init() should take care to invoke enable_usb_clocks() for enabling USB clocks. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: AM43xx: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-28-0/+73
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-28-0/+101
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: OMAP5: added USB initializtion codeKishon Vijay Abraham I2015-08-28-0/+6
| | | | | | | | | Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in omap5 board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: beagle_x15: added USB initializtion codeKishon Vijay Abraham I2015-08-28-1/+1
| | | | | | | | | Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in beagle_x15 board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2Kishon Vijay Abraham I2015-08-28-0/+23
| | | | | | | | Enabled clocks for the second dwc3 controller and second USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: SYS_BOOT fallback logic correction and support for more devicesPaul Kocialkowski2015-08-28-10/+22
| | | | | | | | | | | | | | | | | | | | | The SYS_BOOT-based fallback shouldn't only check for one of the conditions of use and then let the switch/case handle each boot device without enforcing the conditions for each type of boot device again. For instance, this behaviour would trigger the fallback for UART when BOOT_DEVICE_UART is defined, CONFIG_SPL_YMODEM_SUPPORT is enabled (which should be a show-stopper) and e.g. BOOT_DEVICE_USB is enabled and not CONFIG_SPL_USB_SUPPORT. Separating the logic for USB and UART solves this. In addition, this adds support for more peripheral devices (USBETH and CPGMAC) to the fallback mechanism. Note that the USBETH boot device should always be different from the USB boot device (each should match a different bootrom handoff case). Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* arm: spear: Enable caches on SPEArStefan Roese2015-08-28-0/+10
| | | | | | | | | | | The designware ethernet driver supports d-cache now. So there is nothing stopping us now to enable the caches completely on SPEAr. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* arm: spear: Move to common SPL infrastructureStefan Roese2015-08-28-266/+73
| | | | | | | | | | | | | The SPL implementation for SPEAr600 is older than the common SPL infrastructure. This patch now moves the SPEAr600 SPL over to the common SPL code. Tested on the only SPEAr board that currently uses SPL in mainline U-Boot, the x600. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* ARM: k2l: Fix device speedsLokesh Vutla2015-08-28-2/+2
| | | | | | | | | | | ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Build MLO by defaultLokesh Vutla2015-08-28-0/+4
| | | | | | | | | | | MLO(NAND/MMC boot image), is used for all the ks2 platforms. Enabling it in config.mk so that these images will be automatically built upon calling make. u-boot-spi.gph is already the build target, so not including here. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Rename u-boot-nand.gph to MLOLokesh Vutla2015-08-28-2/+4
| | | | | | | | | | | | | | NAND boot mode, ROM expects an image with a gp header in the beginning and an 8bytes filled with zeros at the end. The same is true for SD boot on K2G platforms but the file name should be MLO. Renaming u-boot-nand.gph to MLO, so that same image can be used for NAND and SD boots. And also not including all the u-boot only images under CONFIG_SPL_BUILD. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: move the custom build rules out to keystone specific makefileNishanth Menon2015-08-28-0/+22
| | | | | | | | | | | | | | | Keystone has build rules introduced by commit ef509b9063fb7 ("k2hk: add support for k2hk SOC and EVM") and commit 0e7f2dbac6ead ("keystone: add support for NAND gpheader image"). These are not reused by other platforms for the build, hence there is no clear benefit is maintaining them in the generic makefile as a build target. move these to the keystone specific make option Original idea of using config.mk by Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-28-0/+16
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-28-0/+11
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-08-26-0/+2
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| * mtd: nand: mxs support oobsize bigger than 512Peng Fan2015-08-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ecc chunk data size is 512 and oobsize is bigger than 512, there is a chance that block_mark_bit_offset conflicts with bch ecc area. The following graph is modified from kernel gpmi-nand.c driver with each data block 512 bytes. We can see that Block Mark conflicts with ecc area from bch view. We can enlarge the ecc chunk size to avoid this problem to those oobsize which is larger than 512. | P | |<----------------------------------------------------------------->| | | | (Block Mark) | | P' | | | | |<--------------------------------------------------->| D | | O'| | |<--------->| |<->| V V V V V +---+--------------+-+--------------+-+--------------+-+----------+-+---+ | M | data |E| data |E| data |E| data |E| | +---+--------------+-+--------------+-+--------------+-+----------+-+---+ ^ ^ | O | |<---------------->| P : the page size for BCH module. E : The ECC strength. G : the length of Galois Field. N : The chunk count of per page. M : the metasize of per page. C : the ecc chunk size, aka the "data" above. P': the nand chip's page size. O : the nand chip's oob size. O': the free oob. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com>
* | arm: pxa: clean-up include file orderMarcel Ziswiler2015-08-24-3/+3
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | arm: pxa: use common timer functionsAndrew Ruder2015-08-24-69/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves pxa to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) pxa timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locked the processor. Rather than patch the specific pxa issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
* | pxa: Fix boot hang by avoiding vector relocationAndrew Ruder2015-08-24-0/+24
|/ | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") pxa does not boot anymore. Add a specific relocate_vectors macro that skips the vector relocation, as the pxa SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows pxa to boot again. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
* Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-08-23-34/+769
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig Merged these by hand and re-ran savedefconfig on them. Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: socfpga: Fix SD/MMC boot on ArriaV SoCDKMarek Vasut2015-08-23-0/+6
| | | | | | | | | | | | | | Add the missing DT nodes, so that ArriaV SoCDK can boot from SD card. The SD card must be in slot J5 and BSEL must be 0x5. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: dts: Add bank-name property to each GPIO bankMarek Vasut2015-08-23-0/+3
| | | | | | | | | | | | | | | | Add "bank-name" property to each GPIO bank to give it unique name. The approach here is exactly the same as with the "regulator-name" property for regulators. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Make the pinmux table const u8Marek Vasut2015-08-23-6/+4
| | | | | | | | | | | | | | | | | | | | | | Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Switch to filtered QTS filesMarek Vasut2015-08-23-30/+8
| | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Add qts-filter.sh scriptMarek Vasut2015-08-23-0/+205
| | | | | | | | | | | | | | | | | | Add script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Split Altera socfpga into AV and CV SoCDKMarek Vasut2015-08-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Unbind CPU type from board typeMarek Vasut2015-08-23-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Move wrappers into platform directoryMarek Vasut2015-08-23-0/+545
| | | | | | | | | | | | | | | | | | Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-09-20 21:41:48 +0000