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* treewide: move CONFIG_PHYS_64BIT to KconfigMasahiro Yamada2016-08-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so that it is always available to the build system. Otherwise we can run into cases where we have inconsistent sizes of certain attributes. Ravi Babu reported offset mismatch of struct dwc3 across files since commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t"). Since the commit, resource_addr_t points to phys_addr_t, whose size is dependent on CONFIG_PHYS_64BIT for ARM architecture. I tried my best to use "select" where possible (for example, ARMv8 architecture) because I think this kind of option is generally user- unconfigurable. However, I see some of PowerPC boards have 36BIT defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the defconfigs for such boards. CONFIG_36BIT is no longer referenced, so all of the defines were removed from CONFIG_SYS_EXTRA_OPTIONS. Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Ravi Babu <ravibabu@ti.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARM: Rework and correct barrier definitionsTom Rini2016-08-05-40/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-08-02-44/+41
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| * ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIPHou Zhiqiang2016-08-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | The PPA binary may be stored on QSPI flash instead of NOR. So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code by addition of a new QSPI specific flag. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT nodeHou Zhiqiang2016-08-02-0/+2
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Fixed the backward compatiblity issueHou Zhiqiang2016-08-02-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | Appended the compatible strings of old version PSCI to the latest version supported. And there are some psci functions' property must be added to DT only for psci version 0.1, including cpu_on, cpu_off, cpu_suspend, migrate. Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Removed unused codeHou Zhiqiang2016-08-02-17/+0
| | | | | | | | | | | | | | | | Identify the PSCI node only by its name, so removed the code finding it by compatible string. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-08-02-3/+2
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| * | ARM64: zynqmp: Do not enable DM_MMC by defaultMichal Simek2016-08-02-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch: "dm: mmc: zynq: Convert zynq to use driver model for MMC" (sha1: 329a449f2c289b4de8f892fca1d9379ce5fd81b8) added dependency on enabling some MMC options by default. There are minimal ZynqMP configurations which require only minimal configurations to be enabled to keep u-boot size as lower as possible. Move options to defconfig instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodesMichal Simek2016-08-01-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serial driver is getting clk information via DT that's why also clk node needs to have this flag. Different behavior was introduced by: "dm: Use dm_scan_fdt_dev() directly where possible" (sha1: 911954859d6dece49c3e4835faea004cfe392506) where simple-bus driver starts to call dm_scan_fdt_dev() which has additional logic around pre_reloc_only parameter which exclude clk nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | libfdt: Introduce new ARCH_FIXUP_FDT optionMichal Simek2016-07-31-0/+4
|/ | | | | | | | | | Add new Kconfig option to disable arch_fixup_fdt() calls for cases where U-Boot shouldn't update memory setup in DTB file. One example of usage of this option is to boot OS with different memory setup than U-Boot use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-07-31-19/+1101
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| * rockchip: add support for rk3288 PopMetal boardjk.kernel@gmail.com2016-07-31-0/+593
| | | | | | | | | | | | | | | | | | PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and Gigabit Ethernet. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add basic support for fennec-rk3288 boardjk.kernel@gmail.com2016-07-31-2/+493
| | | | | | | | | | | | | | | | | | | | Fennec is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access to display pins, I2C, SPI, UART and GPIOs. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: move evb board to rockchip folderjk.kernel@gmail.com2016-07-31-1/+1
| | | | | | | | | | | | | | | | The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is the real vendor name. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Revert "rockchip: Move the MMC setup check earlier"jk.kernel@gmail.com2016-07-31-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to setup sdmmc gpio, otherwise we will hit an error below: =>mmc info blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 - -1 0 - found uclass_find_device_by_seq: 0 1 - -1 -1 - -1 0 - not found fdtdec_get_int_array: interrupts get_prop_check_min_len: interrupts Buswidth = 1, clock: 0 Buswidth = 1, clock: 400000 Sending CMD0 dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy This reverts commit 6efeeea79c880d3dd262e0dca9da2687f0ab68c9. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * rockchip: add a dummy byte for the sdram-channel propertyjk.kernel@gmail.com2016-07-31-1/+2
| | | | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * configs: rockchip: remove no use MACROKever Yang2016-07-31-3/+0
| | | | | | | | | | | | | | | | The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | sunxi: Re-enable h3 emac supportHans de Goede2016-07-31-0/+11
|/ | | | | | | | | | | | | | With the recent bug fixes for the sun8i_emac driver all known issues are resolved, so we can re-enable the driver. While at it, also enable the emac on the Orange Pi One. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: am57xx-idk-common: Enable support for QSPIVignesh R2016-07-30-0/+49
| | | | | | | | | | | AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board connected to TI QSPI over CS0. Hence, add QSPI and flash slave DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: dra7xx: Update spi-max-frequency for QSPIVignesh R2016-07-30-2/+2
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz. Therefore update the spi-max-frequency value of QSPI node for DRA74 and DRA72 evm. This increase flash read speed by ~2MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: dra7xx: Change DPLL_PER_HS13 divider valueLokesh Vutla2016-07-30-1/+1
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-3/+44
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| * colibri_imx7: add Colibri iMX7S/iMX7D module supportStefan Agner2016-07-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | This commit adds support for the Toradex Computer on Modules Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence can be easily supported by one board. The board code detects RAM size at runtime which is one of the differences between the two boards. The board also uses the UART's in DTE mode, hence making use of the new DTE support via serial DM. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx7dsabresd_secure_defconfig: Use CONFIG_ARMV7_BOOT_SEC_DEFAULTFabio Estevam2016-07-28-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for introducing MX7_SEC, as there is the CONFIG_ARMV7_BOOT_SEC_DEFAULT option for this purpose. Switch to CONFIG_ARMV7_BOOT_SEC_DEFAULT and get rid of MX7_SEC. Tested by booting a 4.1.15 NXP kernel with mx7dsabresd_secure_defconfig target. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
| * Revert "imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for EXTFS"Breno Lima2016-07-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c1ebf54868359005 ("imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for EXTFS") causes SPL breakage on wandboard: ERROR: v7_dcache_inval_range - start address is not aligned - 0x1820006c ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1820086c ERROR: v7_dcache_inval_range - start address is not aligned - 0x1820006c ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1820086c ** First descriptor is NOT a primary desc on 0:1 ** spl: no partition table found SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### This error is seen when SPL and u-boot.img are stored in the raw SD card partition. This reverts commit c1ebf54868359005c32944c1473668d5fcaca158. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6: clock: Fix the logic for reading axi_alt_selFabio Estevam2016-07-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * Revert "arch-mx6: fix MX6_PAD_DECLARE macro to work with MX6 duallite"Stefano Babic2016-07-20-2/+2
| | | | | | | | | | | | This reverts commit 225126da99dd9ba1478e32468e298085d1e3fb61. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * mx7_common: use Kconfig for ARMv7 non-secure modeStefan Agner2016-07-19-0/+2
| | | | | | | | | | | | | | | | Use existing Kconfig symbols to let the user configure whether to build a U-Boot with non-secure mode support or not. This also allows to enable virtualization extension easily. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx7: set soc environment according to exact SoC typeStefan Agner2016-07-19-0/+14
| | | | | | | | | | | | | | | | This can be useful if the same U-Boot binary is used for boards available with a i.MX 7Solo and i.MX 7Dual. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * imx6: clock: typo fixPeng Fan2016-07-12-1/+1
| | | | | | | | | | | | | | Typo fix, "PPL2 -> PLL2" Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * arch-mx6: fix MX6_PAD_DECLARE macro to work with MX6 dualliteHannes Schmelzer2016-07-12-2/+2
| | | | | | | | | | | | | | if we build for an i.mx6 (d)ual(l)ite CONFIC_MX6DL we shall use MX6DL_PAD instead the common MX6_PAD. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
| * mx7: Place MX7_SEC option in KconfigFabio Estevam2016-07-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MX7_SEC is an existing configuration option that allows booting the kernel in secure mode. Place this option in Kconfig, so that boards can select this option in their defconfig files. Selecting this option is necessary when booting a kernel provided by NXP, such as 3.14_GA and 4.1.15_GA. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Michael Trimarchi <michael@amarulasolutions.com>
| * mx6: Add Phytec PCM058 i.MX6 QuadStefano Babic2016-07-12-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Phytec-i.MX6 SOM with NAND Support: - 1GB RAM - Ethernet - SPI-NOR Flash - NAND (1024 MB) - external SD - UART Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6: add support for el6x boardStefano Babic2016-07-12-0/+13
| | | | | | | | | | | | | | | | | | Custom Board based on MX6 Dual, 1GB RAM and eMMC. There are two variants of the board with and without PCIe (ZC5202 and ZC5601). Signed-off-by: Stefano Babic <sbabic@denx.de>
| * imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for EXTFSPetr Kulhavy2016-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | spl_boot_mode() returned MMCSD_MODE_RAW on MMC if CONFIG_SPL_EXT_SUPPORT was configured. EXTFS is the default filesystem selected in imx6_spl.h and the function should return MMCSD_MODE_FS instead. Fix this and return MMCSD_MODE_FS instead in such cases. Signed-off-by: Petr Kulhavy <brain@jikos.cz> CC: Stefano Babic <sbabic@denx.de> CC: Tim Harvey <tharvey@gateworks.com> CC: Fabio Estevam <Fabio.Estevam@freescale.com>
* | dm: mmc: zynq: Convert zynq to use driver model for MMCSimon Glass2016-07-27-0/+5
| | | | | | | | | | | | | | Move zynq to the latest driver model support by enabling CONFIG_DM_MMC, CONFIG_DM_MMC_OPS and CONFIG_BLK. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: zynq: usb: Convert to CONFIG_DM_USBSimon Glass2016-07-27-0/+2
| | | | | | | | | | | | Convert zynq USB to driver model. Note this is tested on zynq-zybo only. Signed-off-by: Simon Glass <sjg@chromium.org>
* | zynq: Increase the early malloc() sizeSimon Glass2016-07-27-0/+7
| | | | | | | | | | | | This is needed to support driver-model conversion of USB and block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-26-0/+92
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| * | sunxi: Add EMAC ethernet0 alias for H3 dtsiChen-Yu Tsai2016-07-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi ethernet address generation code looks for ethernet[0-3] aliases to find ethernet controllers to generate MAC addresses for. Without a valid address, the driver fails to register. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add defconfig and dts file for the Orange Pi PC Plus SBCHans de Goede2016-07-26-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a new Orange Pi PC *Plus* version available now, this is an extended version of the regular Orange Pi PC with sdio wifi and an eMMC. The upstream kernel devs have decided that they want a separate dts for the PC Plus rather then sharing a single dts between the regular PC and the PC Plus. So add a new orangepi_pc_plus_defconfig to match. The added dts file matches the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-26-71/+543
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| * | | armv8: fsl-layerscape: mmu: Fix enabling MMUYork Sun2016-07-26-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: move secure text section into OCRAMHongbo Zhang2016-07-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-26-2/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: check target CPU ID before further operationsHongbo Zhang2016-07-26-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The input parameter CPU ID needs to be validated before furher oprations such as CPU_ON, this patch introduces the function to do this. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: add PSCI v1.0 functions skeletonHongbo Zhang2016-07-26-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu2016-07-26-3/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl_lsch2: Add SerDes 2 supportQianyu Gong2016-07-26-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-19 06:39:41 +0000