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| * Revert "rockchip: Move the MMC setup check earlier"jk.kernel@gmail.com2016-07-31-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to setup sdmmc gpio, otherwise we will hit an error below: =>mmc info blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 - -1 0 - found uclass_find_device_by_seq: 0 1 - -1 -1 - -1 0 - not found fdtdec_get_int_array: interrupts get_prop_check_min_len: interrupts Buswidth = 1, clock: 0 Buswidth = 1, clock: 400000 Sending CMD0 dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy This reverts commit 6efeeea79c880d3dd262e0dca9da2687f0ab68c9. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * rockchip: add a dummy byte for the sdram-channel propertyjk.kernel@gmail.com2016-07-31-1/+2
| | | | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * configs: rockchip: remove no use MACROKever Yang2016-07-31-3/+0
| | | | | | | | | | | | | | | | The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | sunxi: Re-enable h3 emac supportHans de Goede2016-07-31-0/+11
|/ | | | | | | | | | | | | | With the recent bug fixes for the sun8i_emac driver all known issues are resolved, so we can re-enable the driver. While at it, also enable the emac on the Orange Pi One. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: am57xx-idk-common: Enable support for QSPIVignesh R2016-07-30-0/+49
| | | | | | | | | | | AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board connected to TI QSPI over CS0. Hence, add QSPI and flash slave DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: dts: dra7xx: Update spi-max-frequency for QSPIVignesh R2016-07-30-2/+2
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz. Therefore update the spi-max-frequency value of QSPI node for DRA74 and DRA72 evm. This increase flash read speed by ~2MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: dra7xx: Change DPLL_PER_HS13 divider valueLokesh Vutla2016-07-30-1/+1
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-3/+44
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| * colibri_imx7: add Colibri iMX7S/iMX7D module supportStefan Agner2016-07-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | This commit adds support for the Toradex Computer on Modules Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence can be easily supported by one board. The board code detects RAM size at runtime which is one of the differences between the two boards. The board also uses the UART's in DTE mode, hence making use of the new DTE support via serial DM. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx7dsabresd_secure_defconfig: Use CONFIG_ARMV7_BOOT_SEC_DEFAULTFabio Estevam2016-07-28-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for introducing MX7_SEC, as there is the CONFIG_ARMV7_BOOT_SEC_DEFAULT option for this purpose. Switch to CONFIG_ARMV7_BOOT_SEC_DEFAULT and get rid of MX7_SEC. Tested by booting a 4.1.15 NXP kernel with mx7dsabresd_secure_defconfig target. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
| * Revert "imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for EXTFS"Breno Lima2016-07-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c1ebf54868359005 ("imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for EXTFS") causes SPL breakage on wandboard: ERROR: v7_dcache_inval_range - start address is not aligned - 0x1820006c ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1820086c ERROR: v7_dcache_inval_range - start address is not aligned - 0x1820006c ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1820086c ** First descriptor is NOT a primary desc on 0:1 ** spl: no partition table found SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### This error is seen when SPL and u-boot.img are stored in the raw SD card partition. This reverts commit c1ebf54868359005c32944c1473668d5fcaca158. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6: clock: Fix the logic for reading axi_alt_selFabio Estevam2016-07-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * Revert "arch-mx6: fix MX6_PAD_DECLARE macro to work with MX6 duallite"Stefano Babic2016-07-20-2/+2
| | | | | | | | | | | | This reverts commit 225126da99dd9ba1478e32468e298085d1e3fb61. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * mx7_common: use Kconfig for ARMv7 non-secure modeStefan Agner2016-07-19-0/+2
| | | | | | | | | | | | | | | | Use existing Kconfig symbols to let the user configure whether to build a U-Boot with non-secure mode support or not. This also allows to enable virtualization extension easily. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx7: set soc environment according to exact SoC typeStefan Agner2016-07-19-0/+14
| | | | | | | | | | | | | | | | This can be useful if the same U-Boot binary is used for boards available with a i.MX 7Solo and i.MX 7Dual. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * imx6: clock: typo fixPeng Fan2016-07-12-1/+1
| | | | | | | | | | | | | | Typo fix, "PPL2 -> PLL2" Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * arch-mx6: fix MX6_PAD_DECLARE macro to work with MX6 dualliteHannes Schmelzer2016-07-12-2/+2
| | | | | | | | | | | | | | if we build for an i.mx6 (d)ual(l)ite CONFIC_MX6DL we shall use MX6DL_PAD instead the common MX6_PAD. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
| * mx7: Place MX7_SEC option in KconfigFabio Estevam2016-07-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MX7_SEC is an existing configuration option that allows booting the kernel in secure mode. Place this option in Kconfig, so that boards can select this option in their defconfig files. Selecting this option is necessary when booting a kernel provided by NXP, such as 3.14_GA and 4.1.15_GA. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Michael Trimarchi <michael@amarulasolutions.com>
| * mx6: Add Phytec PCM058 i.MX6 QuadStefano Babic2016-07-12-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Phytec-i.MX6 SOM with NAND Support: - 1GB RAM - Ethernet - SPI-NOR Flash - NAND (1024 MB) - external SD - UART Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6: add support for el6x boardStefano Babic2016-07-12-0/+13
| | | | | | | | | | | | | | | | | | Custom Board based on MX6 Dual, 1GB RAM and eMMC. There are two variants of the board with and without PCIe (ZC5202 and ZC5601). Signed-off-by: Stefano Babic <sbabic@denx.de>
| * imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for EXTFSPetr Kulhavy2016-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | spl_boot_mode() returned MMCSD_MODE_RAW on MMC if CONFIG_SPL_EXT_SUPPORT was configured. EXTFS is the default filesystem selected in imx6_spl.h and the function should return MMCSD_MODE_FS instead. Fix this and return MMCSD_MODE_FS instead in such cases. Signed-off-by: Petr Kulhavy <brain@jikos.cz> CC: Stefano Babic <sbabic@denx.de> CC: Tim Harvey <tharvey@gateworks.com> CC: Fabio Estevam <Fabio.Estevam@freescale.com>
* | dm: mmc: zynq: Convert zynq to use driver model for MMCSimon Glass2016-07-27-0/+5
| | | | | | | | | | | | | | Move zynq to the latest driver model support by enabling CONFIG_DM_MMC, CONFIG_DM_MMC_OPS and CONFIG_BLK. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: zynq: usb: Convert to CONFIG_DM_USBSimon Glass2016-07-27-0/+2
| | | | | | | | | | | | Convert zynq USB to driver model. Note this is tested on zynq-zybo only. Signed-off-by: Simon Glass <sjg@chromium.org>
* | zynq: Increase the early malloc() sizeSimon Glass2016-07-27-0/+7
| | | | | | | | | | | | This is needed to support driver-model conversion of USB and block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-26-0/+92
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| * | sunxi: Add EMAC ethernet0 alias for H3 dtsiChen-Yu Tsai2016-07-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi ethernet address generation code looks for ethernet[0-3] aliases to find ethernet controllers to generate MAC addresses for. Without a valid address, the driver fails to register. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add defconfig and dts file for the Orange Pi PC Plus SBCHans de Goede2016-07-26-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a new Orange Pi PC *Plus* version available now, this is an extended version of the regular Orange Pi PC with sdio wifi and an eMMC. The upstream kernel devs have decided that they want a separate dts for the PC Plus rather then sharing a single dts between the regular PC and the PC Plus. So add a new orangepi_pc_plus_defconfig to match. The added dts file matches the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-26-71/+543
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| * | | armv8: fsl-layerscape: mmu: Fix enabling MMUYork Sun2016-07-26-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: move secure text section into OCRAMHongbo Zhang2016-07-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-26-2/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: ls102xa: check target CPU ID before further operationsHongbo Zhang2016-07-26-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The input parameter CPU ID needs to be validated before furher oprations such as CPU_ON, this patch introduces the function to do this. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | ARMv7: PSCI: add PSCI v1.0 functions skeletonHongbo Zhang2016-07-26-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu2016-07-26-3/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl_lsch2: Add SerDes 2 supportQianyu Gong2016-07-26-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Consolidate the LSCH2 common definesQianyu Gong2016-07-26-39/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common configurations. So put the common define under FSL_LSCH2 to increase readability. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Add A72 core detectionAlison Wang2016-07-26-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | SECURE_BOOT: Enable SD as a source for bootscriptSumit Garg2016-07-26-14/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | SECURE_BOOT: Enable chain of trust in SPL frameworkSumit Garg2016-07-26-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Override jump_to_image_no_args function to include validation of u-boot image using spl_validate_uboot before jumping to u-boot image. Also define macros in SPL framework to enable crypto operations. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | include: usb: Rename USB controller base address mappingRajesh Bhagat2016-07-26-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-07-26-6/+6
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| * | | | omap5/dra7: i2c: correct register offset for sync registerMugunthan V N2016-07-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register offset of i2c_sysc offset is not correct as per omap5[1]/dra7[2] TRM, correct the offsets as per the documentation. [1] - http://www.ti.com/lit/pdf/swpu249 [2] - http://www.ti.com/lit/pdf/spruhz6 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | | omap4: i2c: correct register offset for sync registerMugunthan V N2016-07-26-3/+3
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register offset of i2c_sysc offset is not correct as per omap4 TRM [1], correct the offsets as per the documentation. [1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | rockchip: sdram: Fix register layout for LinuxJohn Keeping2016-07-25-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ChromeOS kernel reads the RAM settings from PMU_SYS_REG2 and expects the bootloader to store the necessary information there. We're using the same register to pass the same information between the SPL and U-Boot but in a slightly different format. Change this to use the format expected by the Linux DMC driver so that the system doesn't hang in Linux by misconfiguring the RAM. This is almost the same as commit b5788dc ("rockchip: rk3288: correct sdram setting") which was reverted in commit b525556 ("Revert "rockchip: rk3288: correct sdram setting"") but parenthese have been added to apply the mask correctly when reading the "bw" setting and a couple of minor style issues have been fixed to keep check_patch.pl happy. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | ARM64: rockchip: add support for rk3399 SoC based evbKever Yang2016-07-25-4/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | dts: add support for Rockchip rk3399 socKever Yang2016-07-25-1/+1134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files are from kernel upstream: "649a371 Add linux-next specific files for 20160616" with some modification need by U-Boot: - chosen with stdout-path to uart2. - add clock-frequency for uart2 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | rockchip: Use rockchip_get_clk() to obtain the SoC clockSimon Glass2016-07-25-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code picks the first available clock. In U-Boot proper this is the oscillator device, not the SoC clock device. As a result the HDMI display does not work. Fix this by calling rockchip_get_clk() instead. Fixes: 135aa950 (clk: convert API to match reset/mailbox style) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* | | | rockchip: Add a way to obtain the main clock deviceSimon Glass2016-07-25-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Rockchip SoCs we typically have a main clock device that uses the Soc clock driver. There is also a fixed clock for the oscillator. Add a function to obtain the core clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | cosmetic: rockchip: rk3288: rename rkclk_configure_cpuHeiko Stübner2016-07-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* | | | cosmetic: rockchip: sort socs according to numbersHeiko Stübner2016-07-25-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2025-01-05 01:12:58 +0000