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| * | rk3288: add arch_cpu_init for rk3288Kever Yang2016-09-22-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | We do some SoC level one time setting initialization in arch_cpu_init. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: use dummy byte only enable OF_PLATDATAXu Ziyuan2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a condition to determine the rk3288_sdram_channel size. This patch fixes read sdram_channel property failed from DT on rk3288 boards, which not enable OF_PLATDATA. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * | dts: rk3399: add pinctrl for sdmmcKever Yang2016-09-22-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | This patch add pinctrl for sdcard which may not be initialized before uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: add driver for rk3399Kever Yang2016-09-22-0/+321
| | | | | | | | | | | | | | | | | | | | | This patch add pinctrl driver for rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rk3399: syscon: add support for pmugrfKever Yang2016-09-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | pmugrf is a module like grf which contain some of the iomux registers and other registers. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-09-22-203/+374
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| * | | ARM: dts: uniphier: sync clock/reset controller nodes with LinuxMasahiro Yamada2016-09-23-181/+301
| | | | | | | | | | | | | | | | | | | | | | | | Sync device trees with Linux for easier DT life. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: uniphier: add PLL init code for LD11 SoCMasahiro Yamada2016-09-23-7/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: uniphier: move CONFIG_SPL_* to defconfig or selectMasahiro Yamada2016-09-23-15/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As I repeated in the ML, I am unhappy with config entries with bare defaults. Kick them out of arch/arm/mach-uniphier/Kconfig. Currently, CONFIG_SPL_SERIAL_SUPPORT is not user-configurable (build fails without it), but it should be fixed later anyway, so I am moving CONFIG_SPL_SERIAL_SUPPORT to defconfigs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM64: zynqmp: Fix USB ulpi phy sequenceMichal Simek2016-09-22-4/+0
| | | | | | | | | | | | | | | | | | | | | It should be enough to call low(5us)->high pulse for all cases to provide proper reset. There is no need to call high->low->high. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Add support for USB ulpi phy reset via mode pinsMichal Simek2016-09-22-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mode pins can be used as output for reset. Xilinx boards are using this feature as additional way how to reset USB phys and also others chips on the boards. Mode1 is used on all these boards for this feature. Let SPL toggle reset on this pin by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Add support for DFU from SPLMichal Simek2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL needs to have bigger stack size because of USB. Simple malloc needs to be disabled because dfu code requires different allocation functions. There is no space in OCM that's why random place in DDR is used. BOOTD must be disabled because it is causing compilation error. All variables are disabled and used only variables valid for DFU because they are simple huge. Including automatic variables added by CONFIG_ENV_VARS_UBOOT_CONFIG. Hardcode addresses for u-boot, atf, kernel and dtb just for SPL DFU code. Enable SPL DFU for zcu100. Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM: Add new BOOT_DEVICE_DFU boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | This enum is needed when SPL_DFU is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Add USB boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | Add USB boot mode. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-09-22-0/+57
|/ / | | | | | | | | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-09-18-1025/+1148
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| * | ARM: uniphier: update DRAM init code for LD20 SoCMasahiro Yamada2016-09-19-62/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import the latest version from the Diag software. - Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add PLL init code for LD20 SoCMasahiro Yamada2016-09-19-5/+234
| | | | | | | | | | | | | | | | | | | | | | | | Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: collect clock/PLL init code into a single directoryMasahiro Yamada2016-09-19-24/+18
| | | | | | | | | | | | | | | | | | | | | | | | Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move PLL init code to U-Boot proper where possibleMasahiro Yamada2016-09-19-495/+365
| | | | | | | | | | | | | | | | | | | | | | | | The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PERMasahiro Yamada2016-09-18-1/+1
| | | | | | | | | | | | | | | | | | Basically, this should not be configured by users. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20Masahiro Yamada2016-09-18-31/+10
| | | | | | | | | | | | | | | | | | | | | This is the last code in the mach-uniphier/pinctrl/ directory. Push the remaining code out to delete the directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20Masahiro Yamada2016-09-18-44/+5
| | | | | | | | | | | | | | | | | | | | | Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: include System Bus pin group node in SPL DTMasahiro Yamada2016-09-18-0/+8
| | | | | | | | | | | | | | | | | | | | | This will be needed for setting up the System Bus pin-mux via the LD11/LD20 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: consolidate NAND pin-mux settingsMasahiro Yamada2016-09-18-274/+51
| | | | | | | | | | | | | | | | | | | | | | | | The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove ad-hoc pin-mux code for sLD3Masahiro Yamada2016-09-18-58/+0
| | | | | | | | | | | | | | | | | | These settings are nicely cared by the pinctrl driver now. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoCMasahiro Yamada2016-09-18-2/+0
| | | | | | | | | | | | | | | | | | This is enabled by default for all the supported boot modes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: select PINCTRL and SPL_PINCTRLMasahiro Yamada2016-09-18-0/+2
| | | | | | | | | | | | | | | | | | | | | Now all UniPhier SoCs support a pinctrl driver. Select (SPL_)PINCTRL since it is mandatory even for base use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: add pinctrl device node and pinctrl propertiesMasahiro Yamada2016-09-18-0/+43
| | | | | | | | | | | | | | | | | | DT-side updates to make pinctrl on sLD3 SoC really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21Masahiro Yamada2016-09-17-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, this SoC needs per-board adjustment between clock and address/command lines. This flag will be passed to the DRAM init function and used for compensating the difference of DRAM timing parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: fix DRAM size of LD21 SoC packageMasahiro Yamada2016-09-17-1/+1
| | | | | | | | | | | | | | | | | | The channel 0 DRAM size of LD21 is half of that of LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: merge board init functions into board_init()Masahiro Yamada2016-09-14-40/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the UniPhier platform calls several init functions in the following order: [1] spl_board_init() [2] board_early_init_f() [3] board_init() [4] board_early_init_r() [5] board_late_init() The serial console is not ready at the point of [2], so we want to avoid using [2] from the view point of debuggability. Fortunately, all of the initialization in [2] can be delayed until [3]. I see no good reason to split into [3] and [4]. So, merge [2] through [4]. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: use checkboard() instead of misc_init_f()Masahiro Yamada2016-09-14-24/+7
| | | | | | | | | | | | | | | | | | | | | We can use checkboard() stub to show additional board information, so misc_init_f() should not be used for this purpose. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove IECTRL setup code of LD4 SoCMasahiro Yamada2016-09-14-6/+0
| | | | | | | | | | | | | | | | | | This should be handled by the pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: uniphier-sd: migrate to CONFIG_BLKMasahiro Yamada2016-09-14-0/+1
| | | | | | | | | | | | | | | | | | | | | This is the state-of-the-art MMC driver implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ARM: uniphier: delete unnecessary xHCI pin-mux settingsMasahiro Yamada2016-09-14-48/+0
| | | | | | | | | | | | | | | | | | | | | These ad-hoc pinmux settings were used for the legacy xHCI driver, which has gone now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | usb: uniphier: remove UniPhier xHCI driver and select DM_USBMasahiro Yamada2016-09-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver has not been converted to Driver Model, and it is an obstacle to migrate other block device drivers. Remove it for now. The UniPhier SoCs already use a DM-based EHCI driver, so now ARCH_UNIPHIER can select DM_USB. These two changes must be done atomically because removing the legacy driver causes a build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | ARM: uniphier: sort select:s alphabeticallyMasahiro Yamada2016-09-14-7/+7
| |/ | | | | | | | | | | | | ARCH_UNIPHIER is having more and more select:s. Sort them in case a select is accidentally duplicated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-sunxiTom Rini2016-09-18-9/+127
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| * | sunxi: Add defconfig and dts for the NanoPi NEOJelle van der Waa2016-09-18-1/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb and one usb OTG connector. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: musb: Power off OTG port VBUS when disabledChen-Yu Tsai2016-09-17-8/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel musb driver expects VBUS to be off while initializing musb. Having it on results in a repeating string of warnings, followed by an unusable peripheral. The peripheral is only usable after physically removing the OTG adapter, letting musb reset its state. This partially reverts commit c9f8947e6604 ("sunxi: usb-phy: Never power off the usb ports") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Convert CONFIG_SPL_WATCHDOG_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SPI_SUPPORT to KconfigSimon Glass2016-09-16-0/+9
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SPI_FLASH_SUPPORT to KconfigSimon Glass2016-09-16-0/+9
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass2016-09-16-0/+30
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_POWER_SUPPORT to KconfigSimon Glass2016-09-16-0/+9
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_NAND_SUPPORT to KconfigSimon Glass2016-09-16-0/+15
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_MMC_SUPPORT to KconfigSimon Glass2016-09-16-0/+24
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_LIBGENERIC_SUPPORT to KconfigSimon Glass2016-09-16-0/+30
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_LIBDISK_SUPPORT to KconfigSimon Glass2016-09-16-0/+18
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-04 18:39:20 +0000