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* ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-12-4/+8
| | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add is_dra72x cpu check definitionLokesh Vutla2015-06-12-0/+7
| | | | | | | | | A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+11
| | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+16
| | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-12-24/+207
| | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-06-11-20/+49
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| * dm: usb: tegra: Drop legacy USB codeSimon Glass2015-06-10-3/+0
| | | | | | | | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: Disable device tree for SPL on all boardsSimon Glass2015-06-10-0/+15
| | | | | | | | | | | | | | We plan to enable device tree in SPL by default. Before doing this, explicitly disable it for all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
| * fdt: arm: Drop device tree paddingSimon Glass2015-06-10-1/+2
| | | | | | | | | | | | | | The 4KB padding doesn't seem necessary since we don't normally adjust the control device tree file within U-Boot. Also drop the memory table space. Signed-off-by: Simon Glass <sjg@chromium.org>
| * arm: Allow cleanup_before_linux() without disabling cachesSimon Glass2015-06-10-18/+29
| | | | | | | | | | | | | | | | This function is used before jumping to U-Boot, but in that case we don't always want to disable caches. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
| * dm: tegra: usb: Move USB to driver modelSimon Glass2015-06-10-0/+5
| | | | | | | | | | | | | | | | | | | | Somehow this change was dropped in the various merges. I noticed when I came to turn off the non-driver-model support for Tegra. We need to make this change (and deal with any problems) before going further. Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of http://git.denx.de/u-boot-samsungTom Rini2015-06-10-78/+2
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| * odroid: dts: cleanup of MAX77686 regulatorsPrzemyslaw Marczak2015-06-10-78/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit cleanup MAX77686 regulator node by: - remove the sub-nodes of unconnected regulators - remove the "regulator-compatible" properties of all regulators This prevents printing init errors for the regulators, with duplicated name strings. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-06-10-0/+1
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| * | sunxi: Request macpwr gpio before using itHans de Goede2015-06-10-0/+1
| |/ | | | | | | | | | | | | | | This fixes ethernet no longer working on boards which use a gpio to enable the phy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | tegra: Replace 'Norrin' with 'Nyan-big' and fix typoSimon Glass2015-06-09-1/+1
| | | | | | | | | | | | | | | | With the rename the MAINTAINER file was not updated. Fix it and the 'Chrombook' typo in Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Allow board-specific initSimon Glass2015-06-09-2/+13
| | | | | | | | | | | | | | Add a hook to allows boards to add their own init to board_init(). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Add missing tegra124 peripheralsSimon Glass2015-06-09-7/+7
| | | | | | | | | | | | | | There are some missing entries in the tables. Add them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Introduce SRAM repair on tegra124Simon Glass2015-06-09-1/+31
| | | | | | | | | | | | | | | | This is required in order to avoid instability when running from caches after the kernel starts. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: clock: Adjust PLL access to avoid a warningSimon Glass2015-06-09-2/+5
| | | | | | | | | | | | | | | | A harmless but confusing warning is displayed when looking up the DisplayPort PLL. Correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: clock: Support enabling external clocksSimon Glass2015-06-09-0/+25
| | | | | | | | | | | | | | Add a simple function to enable external clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-bigSimon Glass2015-06-09-0/+3
|/ | | | | | | | | | | | | Enable the EC and keyboard, using the SPI bus. The EC driver requires a particular format and a deactivation delay. Also U-Boot does not support interrupts. For now, adjust the device tree to comply. At some point we should tidy this up to support interrupts and make tegra and exynos use the same setup. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-08-6/+304
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| * imx: drop warning: unused variable 'max_freq'Stefano Babic2015-06-08-1/+2
| | | | | | | | | | | | | | max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * colibri_vf: Enable board specific USB initialisation for USB pen gpioSanchayan Maity2015-06-08-0/+1
| | | | | | | | | | | | | | | | | | | | Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start". Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * vf610: dts: Add device tree supportBhuvanchandra DV2015-06-08-0/+160
| | | | | | | | | | | | | | | | | | Add device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules. Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * arm: vf610: Add iomux support for DSPIBhuvanchandra DV2015-06-08-0/+9
| | | | | | | | | | | | Add iomux definitions for DSPI second instance. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * arm: vf610: Add clock support for DSPIBhuvanchandra DV2015-06-08-0/+12
| | | | | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * colibri_vf: Add pinmux entries for GPIOsBhuvanchandra DV2015-06-08-0/+49
| | | | | | | | | | | | | | | | | | Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs. Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * dm: gpio: vf610: Add GPIO driver supportBhuvanchandra DV2015-06-08-0/+66
| | | | | | | | | | | | Add GPIO driver support to Freescale VF610 Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * mxs: Do not disable bo detection when DC-DC is already enabledStefan Wahren2015-06-01-5/+5
| | | | | | | | | | | | | | | | | | In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns without reenabling brown out detection. So fix this issue by moving the return before brown out deactivation. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * Revert "imx: drop warning: unused variable 'max_freq'"Stefano Babic2015-05-28-2/+1
| | | | | | | | | | | | This reverts commit a0117a5e416629932becf079589f5e1859eab90a. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * imx: drop warning: unused variable 'max_freq'Stefano Babic2015-05-27-1/+2
| | | | | | | | | | | | | | max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | sunxi: Add a proper dts file for the ga10h a33 based tabletHans de Goede2015-06-05-0/+126
| | | | | | | | | | | | | | | | Add and use a proper dts for the ga10h a33 based tablet, as submitted upstream. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Sync dts files with the linux kernelHans de Goede2015-06-04-1102/+1506
| | | | | | | | | | | | | | | | | | | | | | | | Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2 , this gives us a proper dtsi file for the A33 rather then abusing sun8i-a23.dtsi for this. And this replaces our minimal (dummy) sun7i-a20-mk808c and sun8i-a33-astar-mid756 dts files with proper ones. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Add new Mele_A1000G_quad defconfigHans de Goede2015-06-04-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been using the same defconfig (and dts on the kernel side) for both models. Unfortunately this does not work for the otg controller, on the M9 this is routed to a micro-usb connector on the outside, while as on the A1000G-quad it is connected to an usb to sata bridge. This commit adds a new defconfig for the Mele-A1000G-quad to allow using different otg controller settings on the 2 boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: usb_phy: Swap check for disconnect thresholdHans de Goede2015-06-04-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit the code for determining the disconnect threshold was checking for sun4i or sun6i assuming that those where the exception and that newer SoCs use a disconnect threshold of 2 like sun7i does. But it turns out that newer SoCs actually use a disconnect threshold of 3 and sun5i and sun7i are the exceptions, so check for those instead. Here are the settings from the various Allwinner SDK sources: sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); Note this commit makes no functional changes for sun4i - sun7i, and changes the disconnect threshold for sun8i to match what Allwinner uses. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-06-01-0/+26
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| * | arm: rmobile: alt: Update to QoS revision 0.31 and 0.321Nobuhiro Iwamatsu2015-06-01-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: gose: Update to QoS revision 0.311Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7793 QoS to revision 0.311. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: koelsch: Update to QoS revision 0.411Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7791 QoS to revision 0.411. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Update to QoS revision 0.973Nobuhiro Iwamatsu2015-06-01-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7790 QoS to revision 0.973. This commit can changed from KConfig to fit contents of the QoS. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-05-30-146/+98
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| * | | ARM: UniPhier: add pin mux setting for NAND CS1 of PH1-Pro4Masahiro Yamada2015-05-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The chip select 1 of the NAND controller is available if you want to use, although the pins are shared with UART port 2. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: UniPhier: fix pin mux setting for USB port 2 of PH1-sLD8Masahiro Yamada2015-05-31-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The register value should be 1, not 4. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: UniPhier: update DDR PHY register map for PH1-Pro5Masahiro Yamada2015-05-31-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-Pro5 includes a newer version of DDR PHY IP. Some registers have been added to the reserved areas. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: UniPhier: set MACH_PH1_PRO4 as default SoCMasahiro Yamada2015-05-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One disadvantage of commit a26cd04920dc (arch: Make board selection choices optional) is that Kconfig could create such an insane .config file that no board is selected. As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the "optional" again in favor of PH1-Pro4 as the default SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: UniPhier: remove meaningless CONFIG_SPL_BUILD ifdefsMasahiro Yamada2015-05-31-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file is only built for SPL. These ifdef conditionals are unnecessary because UniPhier platform now supports UART on SPL. Show appropriate messages on error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: UniPhier: remove unnecessary cache coherency codeMasahiro Yamada2015-05-31-23/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache coherency for SMP is cared by Linux. In U-Boot, the secondary CPU(s) are just sleeping. Nothing in memory is shared with the primary CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: UniPhier: use 32 bit register access for debug UART settingMasahiro Yamada2015-05-31-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the same reason as commit d0c47b3ef7c5 (serial: UniPhier: use 32 bit register access), use "str" instead of "strb" for the LCR register setting. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-12 00:48:28 +0000