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* Merge branch 'microblaze' of git://git.denx.de/u-boot-microblazeTom Rini2015-02-09-1/+0
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| * common: Move dram_init() declaration to common locationMichal Simek2015-02-09-1/+0
| | | | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-02-06-0/+2295
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| * | arm: mvebu: Add Serdes PHY config codeStefan Roese2015-02-06-0/+2114
| | | | | | | | | | | | | | | | | | | | | | | | | | | This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: armada-xp: Add SPL support used to include the DDR training codeStefan Roese2015-02-06-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPL support to the Marvell Armada-XP. With this addition the bin_hdr integration is not needed any more. The SPL will first initialize the serdes/PHY and the call the DDR setup and training code now integrated into mainline U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-BootStefan Roese2015-02-06-0/+1
| | | | | | | | | | | | | | | | | | | | | This patch adds SPL support to the db-mv784mp-gp eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: maxbcm: Enable SPL to include DDR training code into U-BootStefan Roese2015-02-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPL support to the maxbcm MV78460 based board. Including the fixed DDR configuratrion needed for the DDR training code. And the the serdes PHY init code. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: armada-xp: Change built target to include the SPL binary as bin_hdrStefan Roese2015-02-06-0/+4
| |/ | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
* | ARM: UniPhier: leave the last element of boot_device_table emptyMasahiro Yamada2015-02-07-2/+2
| | | | | | | | | | | | | | | | Checking if the pointer is NULL would be easier to know the tail of the boot_device_table[] array. For clarification, add the /* sentinel */ comment. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: refactor pinmon commandMasahiro Yamada2015-02-07-12/+9
| | | | | | | | | | | | | | | | | | | | The return value of get_boot_mode_sel() is used as the index of the boot_device_table[] array. Its type should be "int" rather than "u32". Use only the iterator "i" for the loop in do_pinmon(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: enable I2C input pins for PH1-sLD8Masahiro Yamada2015-02-07-0/+9
| | | | | | | | | | | | | | To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0) and bit 11 (SCL1/SDA1) of IECTRL register must be set. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: do not compile unnecessary objectsMasahiro Yamada2015-02-07-32/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | It is true that unused functions are removed from the ELF image by the compiler's garbage collection but relying on it too much does not look nice. Currently, the build is taking more than it should. Refactor the makefiles to compile only files that are really needed. CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the optimization. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: remove unused checkboard() functionsMasahiro Yamada2015-02-07-51/+0
| | | | | | | | | | | | | | | | | | | | | | Since commit 0365ffcc0bd6 (generic-board: show model name in board_init_f() too), checkboard() is invoked only when show_board_info() fails to get the model name from Device Tree. It never happens because UniPhier SoCs now only work with CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees have the "model" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: revive support card infoMasahiro Yamada2015-02-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Since commit 0365ffcc0bd6 (generic-board: show model name in board_init_f() too), the support card information has not been displayed because check_support_card() is invoked only when show_board_info() fails to get the model name from Device Tree. This commit adds misc_init_f() function to call check_support_card() from there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: move SPL init functions to spl_board_init()Masahiro Yamada2015-02-07-72/+48
| | | | | | | | | | | | | | | | Now init functions called from board_postclk_init() and dram_init() are only necessary for SPL. Move them to spl_board_init() for clean-up. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: move pin_init() to board_early_init_f()Masahiro Yamada2015-02-07-6/+26
| | | | | | | | | | | | | | Currently, I/O pin settings are not necessary for SPL. The board_early_init_f() seems a suitable place to call pin_init(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: set I2C offset length of on-board EEPROM in DTSMasahiro Yamada2015-02-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The EEPROM chips on UniPhier reference daughter boards expect 2-byte offset address. Since 7132b9fd68a1 (dm: i2c: dts: Support an offset-len device tree property), I2C sub-nodes can have "u-boot,i2c-offset-len" property. It is convenient to set the default I2C offset address length in Device Tree, so that we do not have to set it on the command line. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: move EEPROM device node into a separate DTSMasahiro Yamada2015-02-07-20/+23
| | | | | | | | | | | | | | | | | | This EEPROM chip is installed on the expansion board commonly used on UniPhier platform. To avoid duplicated description, move the EEPROM node to a separate file and include it from other device tree sources. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: remove dummy gpio.hMasahiro Yamada2015-02-07-6/+0
|/ | | | | | | | | | This dummy header was introduced by commit 630bf80ebb34 (ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL). Thanks to commit a08d643dbd85 (dm: Drop gpio.h header from fdtdec.c), such an ugly workaround is no longer needed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2015-02-02-47/+227
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| * davinci: Do not duplicate setting of gdTom Rini2015-01-29-16/+1
| | | | | | | | | | | | | | | | | | | | In f0c3a6c we stopped setting gd in board_init_f, but later had to revert to due problems on certain platforms. As davinci does not look to have these problems, we can drop the setting here and rely upon crt0.S to do it. Cc: Peter Howard <pjh@northern-ridge.com.au> Signed-off-by: Tom Rini <trini@ti.com>
| * omap3: add some MUX definitions for upcoming cairoAlbert ARIBAUD \(3ADEV\)2015-01-29-2/+49
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: mmc: add 1.8v bias setting for MMC1Albert ARIBAUD \(3ADEV\)2015-01-29-0/+1
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: add SDRC settings for Samsung K4X51163PGAlbert ARIBAUD \(3ADEV\)2015-01-29-0/+43
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: make SDRC SHARING setting configurableAlbert ARIBAUD \(3ADEV\)2015-01-29-1/+6
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: enable GP9 timer and UART2Albert ARIBAUD \(3ADEV\)2015-01-29-0/+9
| | | | | | | | | | | | These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-29-28/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2015-02-02-7/+39
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| * | sunxi: rsb: Move rsb_set_device_mode() call to rsb_init()Hans de Goede2015-02-02-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | It turns out that the device_mode_data is rsb specific, rather then slave specific, so integrate the rsb_set_device_mode() call into rsb_init(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi: rsb: Add sun9i (A80 support)Hans de Goede2015-02-02-2/+25
| | | | | | | | | | | | | | | | | | | | | Add support for the A80 to the rsb code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig optionHans de Goede2015-02-02-0/+4
| |/ | | | | | | | | | | | | | | And use this to set the GMAC Transmit Clock Delay Chain value on Banana boards, rather then keying of CONFIG_TARGET_FOO. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2015-01-30-163/+203
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| * | dm: exynos: dts: Set the offset length for cros_ecSimon Glass2015-01-29-0/+1
| | | | | | | | | | | | | | | | | | The EC has no concept of offset, so use a value of 0. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | odroid u3: dts: add missing i2c aliasesPrzemyslaw Marczak2015-01-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This change fixes i2c bus numbering for Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos5: pinmux: check flag for i2c configPrzemyslaw Marczak2015-01-29-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some versions of Exynos5 supports High-Speed I2C, on few interfaces, this change allows support this. The new flag is: PINMUX_FLAG_HS_MODE Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | arndale: dts: add missing i2c aliasesPrzemyslaw Marczak2015-01-29-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this alias setting, the seq numbers of the i2c devices are wrong. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos4: dts: add missing i2c propertiesPrzemyslaw Marczak2015-01-29-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modify i2c nodes in exynos4.dtsi with: - adding proper interrupts arrays for each i2c node, which allows to decode periph id - add reg address for each i2c node for i2c driver internal use Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * | dm: i2c: Provide an offset length parameter where neededSimon Glass2015-01-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * | dm: exynos: dts: Use GPIO bank phandles for GPIOsSimon Glass2015-01-29-39/+30
| | | | | | | | | | | | | | | | | | | | | | | | U-Boot now supports using GPIOs using bank phandles instead of global numbers. Update the exynos device tree files to use this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOsSimon Glass2015-01-29-85/+109
| | | | | | | | | | | | | | | | | | This new method is much easier and matches the kernel. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-3/+4
| | | | | | | | | | | | | | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: zynq: Remove inline gpio functionsSimon Glass2015-01-29-15/+0
| | | | | | | | | | | | | | | | | | | | | These functions serve no useful purpose, and conflict with the generic API. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: tegra: video: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-4/+5
| |/ | | | | | | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: armv7 fix spelling of SCTRLPeng Fan2015-01-30-4/+4
| | | | | | | | | | | | | | SCTLR is the abbreviation of System Control Register, so we should use SCTLR but not SCTRL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | vexpress64: support the Juno Development PlatformLinus Walleij2015-01-30-0/+4
| | | | | | | | | | | | | | | | | | | | The Juno Development Platform is a physical Versatile Express device with some differences from the emulated semihosting models. The main difference is that the system is split in a SoC and an FPGA where the SoC hosts the serial ports at totally different adresses. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | vexpress64: get rid of CONFIG_SYS_EXTRA_OPTIONSLinus Walleij2015-01-30-1/+13
|/ | | | | | | | | | | | | | | | | | | | The Versatile Express ARMv8 semihosted FVP platform is still using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure some compile-time flags. Get rid of this and create a Kconfig entry for the FVP model, and a selectable bool for the semihosting library. The FVP subboard is now modeled as a target choice so we can eventually choose between different ARMv8 versatile express boards (FVP, base model, Juno...) this way. All dependent symbols are updated to reflect this. The 64bit Versatile Express board symbols are renamed VEXPRESS64 so we have some chance to see what is actually going on. Tested on the FVP fast model. Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-1/+21
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| * ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * ARM: atmel: sama5d4: add usb platform dataBo Shen2015-01-19-1/+1
| | | | | | | | | | | | The SAMA5D4 has the same usb platform data with SAMA5D3 SoC. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
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