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* lpc32xx: devkit3250: add spl build supportVladimir Zapolskiy2015-08-12-0/+1
| | | | | | | | | | | | The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND. All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* nand: lpc32xx: add SLC NAND controller supportVladimir Zapolskiy2015-08-12-0/+9
| | | | | | | | | | | | | | | | | | | | | The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* arm: bcmcygnus: Enable Ethernet supportJiandong Zheng2015-08-12-0/+11
| | | | | | | | Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* arm, at91: support for sam9260 based smartweb boardHeiko Schocher2015-08-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for the at91sam9260 based board smartweb from siemens. SPL is used without serial support, as this SoC has only 4k sram for running SPL. Here a U-Boot bootlog: RomBOOT > U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200) CPU: AT91SAM9260 Crystal frequency: 18.432 MHz CPU clock : 198.656 MHz Master clock : 99.328 MHz Watchdog enabled DRAM: 64 MiB WARNING: Caches not enabled NAND: 256 MiB In: serial Out: serial Err: serial Net: macb0 Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Heiko Schocher <hs@denx.de>
* spl, common, serial: build SPL without serial supportHeiko Schocher2015-08-12-4/+7
| | | | | | | | | This patch enables building SPL without CONFIG_SPL_SERIAL_SUPPORT support. Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Ensure we build arch/arm/imx-common on mx28] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-08-6/+53
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| * sunxi: display: Add a few extra register and constant definesHans de Goede2015-08-08-6/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a few extra sunxi display registers and constant defines. Also rename some existing defines (e.g. dropping _GCTRL) and make some more generic (e.g. dropping the 2x scaling from SUNXI_LCDC_TCON1_TIMING_V_TOTAL). This is a preparation patch for adding composite video out support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: usb-phy: Never power off the usb portsHans de Goede2015-08-08-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB devices are not really designed to get the power bounced off and on at them. Esp. USB powered harddisks do not like this. Currently we power off the USB ports both on a "usb reset" and when booting the kernel, causing the usb-power to bounce off and then back on again. This patch removes the powering off calls, fixing the undesirable power bouncing. Note this requires some special handling for the OTG port: 1) We must skip the external vbus check if we've already enabled our own vbus to avoid false positives 2) If on an usb reset we no longer detect that the id-pin is grounded, turn off vbus as that means an external vbus may be present now Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: nand: Add pinmux and clock settings for NAND supportKarol Gugala2015-08-08-0/+3
| | | | | | | | | | | | | | | | | | | | To enable NAND flash in sunxi SPL, pins 0-6, 8-22 and 24 on port C are configured. Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | arm: socfpga: misc: Add support for printing FPGA typeDinh Nguyen2015-08-08-2/+65
| | | | | | | | | | | | | | | | | | | | Add code which uses the new functions for obtaining FPGA ID from the scan manager. This new code prints the FPGA model attached to the SoCFPGA during boot and sets environment variable "fpgatype", which can be used to determine the FPGA model in U-Boot scripts. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Add code to get FPGA IDDinh Nguyen2015-08-08-0/+56
| | | | | | | | | | | | | | Add code to get the FPGA type for Altera's SoCFPGA family of FPGA. The code uses the scan manager to send jtag pulses that will return the FPGA ID. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: scan: Factor out IO chain programmingMarek Vasut2015-08-08-71/+42
| | | | | | | | | | | | | | | | Factor out the code which sends JTAG instruction followed by data into separate function to tidy the code up a little. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: scan: Clean up horrible macrosMarek Vasut2015-08-08-72/+17
| | | | | | | | | | | | | | | | | | | | | | Clean up the horrible macros present in the scan_manager.h . Firstly, the function scan_mgr_io_scan_chain_prg() is static, yet all the macros are used only within it, thus there is no point in having them in the header file. Moreover, the macros are just making the code much less readable, so remove them instead. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: scan: Introduce generic JTAG accessorMarek Vasut2015-08-08-41/+63
| | | | | | | | | | | | | | | | | | Introduce generic function for accessing the JTAG scan chains in the SCC manager. Make use of this function throughout the SCC manager to replace the ad-hoc writes to registers and make the code less cryptic. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: scan: Clean up scan_chain_engine_is_idle()Marek Vasut2015-08-08-28/+34
| | | | | | | | | | | | | | | | | | | | Rework this function so it's clear that it is only polling for certain bits to be cleared. Add kerneldoc. Fix it's return value to be either 0 on success and -ETIMEDOUT on error and propagate this through the scan manager code. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut2015-08-08-0/+17
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_misc_config to wrap the remaining misc configuration values in board file. Again, introduce a function, socfpga_get_sdram_misc_config(), which returns this the structure. This is almost the final step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut2015-08-08-0/+19
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_io_config to wrap the IO configuration values in board file. Introduce socfpga_get_sdram_io_config() function, which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut2015-08-08-0/+64
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager configuration values in board file. Introduce a complementary function, socfpga_get_sdram_rwmgr_config(), which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_initMarek Vasut2015-08-08-0/+3
| | | | | | | | | | | | | | | | | | | | Introduce two wrapper functions, socfpga_get_seq_ac_init() and socfpga_get_seq_inst_init() to avoid direct inclusion of the sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS generated files. This reduces namespace pollution again. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Clean up mach/sdram.hMarek Vasut2015-08-08-3/+1
| | | | | | | | | | | | | | | | Zap non-existent functions and place function prototypes at the beginning of the header file. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sdram: Introduce socfpga_sdram_get_config()Marek Vasut2015-08-08-0/+42
| | | | | | | | | | | | | | | | | | | | Introduce socfpga_sdram_get_config() function implement in a board file, which returns the socfpga_sdram_config structure. This is the last step in cleaning up the socfpga_mmr_init_full(), but not the last step which allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* | ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8Marek Vasut2015-08-08-1/+1
| | | | | | | | | | | | Fix the return value so that standard errno return values can be used. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: Add temporary workaround for missing SD/MMC patchesMarek Vasut2015-08-08-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add a small workaround into the platform code which forces the SDMMC into 8-bit mode (the default configuration for all socfpga platforms) to work around breakage caused by missing patches in mainline which switch the probing of SD/MMC to OF instead of static configuraiton. The patches will hit mainline after the SPL series, so to avoid build issues, add this small temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de>
* | ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESSMarek Vasut2015-08-08-1/+1
| | | | | | | | | | | | | | Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS in the code. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Move SPL GD and malloc to RAMMarek Vasut2015-08-08-0/+3
| | | | | | | | | | | | | | | | | | | | | | Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: misc: Reset ethernet from OFMarek Vasut2015-08-08-19/+49
| | | | | | | | | | | | | | | | | | | | | | Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Probe ethernet GMAC from OFMarek Vasut2015-08-08-3/+1
| | | | | | | | | | | | | | | | | | The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Export bootmode into environment variableMarek Vasut2015-08-08-11/+23
| | | | | | | | | | | | | | | | setenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: misc: Add support for printing boot modeMarek Vasut2015-08-08-0/+13
| | | | | | | | | | | | | | Add support for printing from which device the SoCFPGA board booted. This decodes the BSEL settings and prints it in human readable form. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: misc: Fix warm resetMarek Vasut2015-08-08-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Write necessary magic value into the Warm Boot from ON-Chip RAM group Enable register to enable Warm reset support. Instead of doing this in the reset_cpu() function, we do it in arch early init to avoid breaking old kernel code which expects this magic value to be already written into this register. This magic is originally excavated from common/spl/spl.c in the u-boot port from altera, where this value was written just before the SPL jumped to actual U-Boot in the RAM. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for selecting boot device from BSELMarek Vasut2015-08-08-12/+23
| | | | | | | | | | | | | | | | Rework spl_boot_device() such that it reads the BSEL settings from system manager and decides from where to load U-Boot based on this information. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from QSPIMarek Vasut2015-08-08-1/+4
| | | | | | | | | | | | | | Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from SD/MMCMarek Vasut2015-08-08-0/+17
| | | | | | | | | | | | | | | | | | | | Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Remove custom linker scriptMarek Vasut2015-08-08-45/+0
| | | | | | | | | | | | | | | | Remove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Merge spl_board_init() into board_init_f()Marek Vasut2015-08-08-17/+12
| | | | | | | | | | | | | | | | | | | | The code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add missing reset logicMarek Vasut2015-08-08-1/+9
| | | | | | | | | | | | | | | | Make sure that all the peripherals are correctly reset and then brought out of reset in the SPL. Not going through proper reset cycle might leave the IP blocks in inconsistent state. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Configure SCU and NIC-301 earlyMarek Vasut2015-08-08-0/+22
| | | | | | | | | | | | | | | | | | Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register must be configured, so we can access all peripherals. The NIC-301 must be configured so that the BootROM is not mapped into the SDRAM address space. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Toggle warm reset config I/O bitMarek Vasut2015-08-08-0/+5
| | | | | | | | | | | | | | Synchronise the SPL behavior with the original Altera code and toggle the Warm Reset Config I/O bit accordingly. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()Marek Vasut2015-08-08-5/+9
| | | | | | | | | | | | | | | | Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(), which allows both enabling and disabling the warm reset config I/O functionality. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-31/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg()Marek Vasut2015-08-08-13/+26
| | | | | | | | | | | | | | | | | | It is sufficient to pass in the scan chain ID into the function to determine the remaining two parameters, so drop those params and determine them locally in the function. The big-ish switch in the function is temporary and will be replaced by a proper function call in subsequent patch. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()Marek Vasut2015-08-08-16/+9
| | | | | | | | | | | | | | | | This function is never used outside of scan_manager.c , so make it static. Zap the prototype in scan_manager.h and move the documentation above the function. Make the documentation kerneldoc compliant. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-126/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: clock: Get rid of cm_config_t typedefMarek Vasut2015-08-08-5/+5
| | | | | | | | | | | | Get rid of this cryptic typedef and replace it with explicit struct cm_config. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Add SDMMC, QSPI and DMA definesMarek Vasut2015-08-08-0/+3
| | | | | | | | | | | | | | Add SDMMC, QSPI and DMA reset defines. These are needed by SPL so that we can boot from SD card and QSPI. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Add function to reset add peripheralsMarek Vasut2015-08-08-0/+14
| | | | | | | | | | | | | | Add socfpga_per_reset_all() function to reset all peripherals but the L4 watchdog. This is needed in the SPL. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Repair bridge reset handlingMarek Vasut2015-08-08-4/+4
| | | | | | | | | | | | | | | | | | | | | | The current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and in case it was (!), the code called hang(). This makes no sense at all. Repair it such that the code instead checks whether the FPGA is programmed, but without any polling involved, and only if it is programmed, it de-asserts the reset. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Replace ad-hoc reset functionsMarek Vasut2015-08-08-64/+13
| | | | | | | | | | | | | | | | Replace all those ad-hoc reset functions, which were all copies of the same invocation of clrbits_le32() anyway, with one single unified function, socfpga_per_reset(), with necessary parameters. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Implement unified function to toggle resetMarek Vasut2015-08-08-23/+37
| | | | | | | | | | | | | | | | Implement function socfpga_per_reset(), which allows asserting or de-asserting reset of each reset manager peripheral in a unified manner. Use this function throughout reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-11-11 22:52:08 +0000