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* armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu2016-07-26-3/+200
| | | | | | | | | | | The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl_lsch2: Add SerDes 2 supportQianyu Gong2016-07-26-0/+22
| | | | | | | | | New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Consolidate the LSCH2 common definesQianyu Gong2016-07-26-39/+20
| | | | | | | | | Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common configurations. So put the common define under FSL_LSCH2 to increase readability. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Add A72 core detectionAlison Wang2016-07-26-1/+4
| | | | | | | | | | Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE_BOOT: Enable SD as a source for bootscriptSumit Garg2016-07-26-14/+29
| | | | | | | | | | | Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE_BOOT: Enable chain of trust in SPL frameworkSumit Garg2016-07-26-2/+23
| | | | | | | | | | | Override jump_to_image_no_args function to include validation of u-boot image using spl_validate_uboot before jumping to u-boot image. Also define macros in SPL framework to enable crypto operations. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* include: usb: Rename USB controller base address mappingRajesh Bhagat2016-07-26-9/+7
| | | | | | | | Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARM: uniphier: add clock/reset settings for xHCI of ProXstream2Masahiro Yamada2016-07-24-2/+13
| | | | | | | Deassert resets and enable clock signals of xHCI blocks if the corresponding CONFIG is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add PH1-LD21 board dataMasahiro Yamada2016-07-24-0/+19
| | | | | | | This has the same silicon die as PH1-LD20, but includes DRAM chips in its package. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: introduce flags to uniphier_board_data structureMasahiro Yamada2016-07-24-11/+20
| | | | | | | I need to add more board attributes, so the "flags" member will be handier than separate boolean ones. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename outer-cache register macrosMasahiro Yamada2016-07-24-216/+230
| | | | | | | Sync register macros with Linux code. This will be helpful to develop the counterpart of Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: clear notification flag before L2 operationMasahiro Yamada2016-07-24-6/+6
| | | | | | | Clear the flag immediately before cache operation to not depend on the previous state. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada2016-07-24-21/+19
| | | | | | | | This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: select CONFIG_ARMV8_SPIN_TABLEMasahiro Yamada2016-07-23-0/+1
| | | | | | This is needed when booting Linux without ARM Trusted Firmware. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: renumber serial aliases for Gentil/Vodka boardsMasahiro Yamada2016-07-23-8/+8
| | | | | | | | | | | | On these two boards, the serial0 is used for inter-chip connection, so cannot be used for login console. The serial2 is used instead for them, but it is tedious to use because upper level deployment projects must switch login console per board. [ Linux commit: 2a4a2aadbaad9dffdb564a2895348f3d8e825416 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm: omap5: fix build dependency for secure devicesAndreas Dannenberg2016-07-22-1/+1
| | | | | | | | | | | Commit 17c2987 introduces an undesired dependency on CONFIG_SPL_LOAD_FIT when building U-Boot for AM57xx and DRA7xx high-security (HS) devices that causes the build to break when that option is not active. Fix this issue by only building the u-boot_HS.img target when building U-Boot into an actual FIT image. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: am4x: fix build dependency for secure devicesAndreas Dannenberg2016-07-22-1/+1
| | | | | | | | | | | Commit e29878f introduces an undesired dependency on CONFIG_SPL_LOAD_FIT when building U-Boot for AM43xx high-security (HS) devices that causes the build to break when that option is not active. Fix this issue by only building the u-boot_HS.img target when building U-Boot into an actual FIT image. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8: spl: Call board_init_r from crt0_64 in SPLJeremy Hunt2016-07-22-15/+12
| | | | | | | | | | | | | | | As part of the startup process for boards using the SPL, the meaning of board_init_f changed such that it should return normally rather than calling board_init_r directly. (see db910353a126d84fe8dff7a694ea792f50fcfb6a ) This was fixed in 32-bit arm, but broke when SPL was added to 64 bit arm. This fixes crt0_64 so that it calls board_init_r during the SPL and removes the direct call from board_init_f from the arm SPL example. Signed-off-by: Jeremy Hunt <Jeremy.Hunt@DEShawResearch.com> Acked-by: Simon Glass <sjg@chromium.org>
* armv7: simplify identify_nand_chipLadislav Michl2016-07-22-24/+11
| | | | | | Use newly introduced function Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: armv7: introduce set_gpmc_cs0Ladislav Michl2016-07-22-58/+91
| | | | | | Allow boards to runtime detect flash type. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: make gpmc_cfg constLadislav Michl2016-07-22-9/+6
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> [trini: Adapt am33xx, duovero, omap_zoom1] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* armv7: add reset timeout to identify_nand_chipLadislav Michl2016-07-22-19/+15
| | | | | | | | | | identify_nand_chip hangs forever in loop when NAND is not present. As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout to let function fail gracefully allowing caller to know NAND is not present. On NAND equipped board, reset succeeds on first read, so 1000 loops seems to be safe timeout. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* spl: zImage support in Falcon modeLadislav Michl2016-07-22-32/+42
| | | | | | | | Other payload than uImage is currently considered to be raw U-Boot image. Check also for zImage in Falcon mode. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-07-22-18/+3
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| * ARM64: zynqmp: Remove get_uart_clk()Michal Simek2016-07-22-17/+0
| | | | | | | | | | | | ZynqMP will use reading clock freq directly from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Enable CLK and SPL_CLK by defaultMichal Simek2016-07-22-0/+2
| | | | | | | | | | | | | | Serial driver starts to use clk framework that's why enable it by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * spl: Fix compilation warnings for arm64Michal Simek2016-07-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make code 64bit aware. Warnings: +../arch/arm/lib/spl.c: In function ‘jump_to_image_linux’: +../arch/arm/lib/spl.c:63:3: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] +../common/spl/spl_fat.c: In function ‘spl_load_image_fat’: +../common/spl/spl_fat.c:91:33: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-07-21-25/+886
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| * ARM: tegra: pick up actual memory sizeStephen Warren2016-07-21-12/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra186, U-Boot is booted by the binary firmware as if it were a Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address of that DTB, and parse the /memory/reg property to determine the actual RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use. Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion that U-Boot use that DTB as its control DTB. I don't believe that would work well, so I do not plan to put any effort into this. By default the FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT bindings. U-Boot aims to use only upstreamed DT bindings, or as close as it can get. Replacing this DTB with a DTB using upstream bindings is physically quite easy; simply replace the content of one of the GPT partitions on the eMMC. However, the binary FW at least partially relies on the existence/content of some nodes in the DTB, and that requires the DTB to be written according to downstream bindings. Equally, if U-Boot continues to use appended DTBs built from its own source tree, as it does for all other Tegra platforms, development and deployment is much easier. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: Add save_boot_params for ARMv8Stephen Warren2016-07-21-0/+9
| | | | | | | | | | | | | | | | | | | | | | Implement a hook to allow boards to save boot-time CPU state for later use. When U-Boot is chain-loaded by another bootloader, CPU registers may contain useful information such as system configuration information. This feature mirrors the equivalent ARMv7 feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: add IVC protocol implementationStephen Warren2016-07-21-0/+742
| | | | | | | | | | | | | | | | | | | | | | | | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter Processor Communication) framework. Within the context of U-Boot, it is typically used for communication between the main CPU and various auxiliary processors. In particular, it will be used to communicate with the BPMP (Boot and Power Management Processor) on Tegra186 in order to manipulate clocks and reset signals. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: unify Tegra186 Makefile a bitStephen Warren2016-07-21-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many files in arch/arm/mach-tegra are compiled conditionally based on Kconfig variables, or applicable to all platforms. We can let the main Tegra Makefile handle compiling (or not) those files to avoid each SoC- specific Makefile needing to duplicate entries for those files. This leaves the SoC-specific Makefiles to compile truly SoC-specific code. In the future, we'll hopefully add Kconfig variables for all the other files, and refactor those files, and so reduce the need for SoC-specific Makefiles and/or ifdefs in the Makefiles. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: split p2771-0000 buildStephen Warren2016-07-21-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple versions of p2771-0000 board. There are SW visible incompatible differences between the versions, and they are relevant to U-Boot. Create separate "A02" and "B00" defconfigs (named after the first and/or only board rev the defconfig supports) so that users can select which build they want. With the minimal set of HW currently enabled in U-Boot, the differences are irrelevant, hence the DT files aren't different. However, that will change in a future patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: fix Tegra186 DT GPIO binding headerStephen Warren2016-07-21-1/+1
| | | | | | | | | | | | | | | | Tegra186 uses different GPIO port IDs compared to previous chips. Make sure the SoC DT file includes the correct GPIO binding header. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"Tom Rini2016-07-21-5/+0
|/ | | | | | | | | | Per Vikas' request, the problem this commit is supposed to be solving is something he doesn't see and further this introduces additional hardware requirements. This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-583/+994
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * ARMv8/PSCI: Fixup the device tree for PSCIHou Zhiqiang2016-07-19-64/+159
| | | | | | | | | | | | | | | | Set the enable-method in the cpu node to PSCI, and create device node for PSCI, when PSCI was enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/Layerscape: switch SMP method accordinglyHou Zhiqiang2016-07-19-3/+46
| | | | | | | | | | | | | | | | | | If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/layerscape: Add FSL PPA supportHou Zhiqiang2016-07-19-0/+69
| | | | | | | | | | | | | | | | | | | | | | The FSL Primary Protected Application (PPA) is a software component loaded during boot which runs in TrustZone and remains resident after boot. Use the secure firmware framework to integrate FSL PPA into U-Boot. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8: add the secure monitor firmware frameworkHou Zhiqiang2016-07-19-0/+342
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This framework is introduced for ARMv8 secure monitor mode firmware. The main functions of the framework are, on EL3, verify the firmware, load it to the secure memory and jump into it, and while it returned to U-Boot, do some necessary setups at the 'target exception level' that is determined by the respective secure firmware. So far, the framework support only FIT format image, and need to define the name of which config node should be used in 'configurations' and the name of property for the raw secure firmware image in that config. The FIT image should be stored in Byte accessing memory, such as NOR Flash, or else it should be copied to main memory to use this framework. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: add i/d-cache enable function to enable_cachesHou Zhiqiang2016-07-19-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: Convert to use common MMU frameworkYork Sun2016-07-19-432/+238
| | | | | | | | | | | | | | | | Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: mmu: Add support of non-identical mappingYork Sun2016-07-15-44/+68
| | | | | | | | | | | | | | Introduce virtual and physical addresses in the mapping table. This change have no impact on existing boards because they all use idential mapping. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: mmu: split block if necessaryYork Sun2016-07-15-32/+38
| | | | | | | | | | | | | | | | | | When page tables are created, allow later table to be created on previous block entry. Splitting block feature is already working with current code. This patch only rearranges the code order and adds one condition to call split_block(). Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: mmu: house cleaningYork Sun2016-07-15-5/+10
| | | | | | | | | | | | | | | | Make setup_pgtages() and get_tcr() available for platform code to customize MMU tables. Remove unintentional call of create_table(). Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: Add tlb_allocated to arch global dataYork Sun2016-07-15-0/+1
| | | | | | | | | | | | | | | | | | When secure ram is used, MMU tables have to be put into secure ram. To use common MMU code, gd->arch.tlb_addr will be used to host TLB entry pointer. To save allocated memory for later use, tlb_allocated variable is added to global data structure. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: Move secure_ram variable out of generic global dataYork Sun2016-07-15-10/+24
| | | | | | | | | | | | | | Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
* | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-279/+516
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| * | ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.SChen-Yu Tsai2016-07-15-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a secure data section for storing variables, there should be no need for platform code to get the stack address. Make psci_get_cpu_stack_top a local function, as it should only be used in armv7/psci.S and only by psci_stack_setup. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
generated by cgit v1.1 at 2024-10-12 17:24:02 +0000