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* armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-13-0/+1787
| | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* board: arm:: Add support for Broadcom BCM23550Steve Rae2016-06-13-0/+1963
| | | | | | Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-13-31/+1674
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| * ARM: at91: Fix PMC bit definitionsMarek Vasut2016-06-12-8/+8
| | | | | | | | | | | | | | Add missing parenthesis around the variable into the macro. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91: sama5: Extend boot device autodetectionMarek Vasut2016-06-12-21/+39
| | | | | | | | | | | | | | | | | | | | | | | | Extend the boot device autodetection from SAMA5D2 only to the entire SAMA5Dx family of microcontrollers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [minor compile fix for SAMA5D2] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
| * arm: at91: Add support for gurnardAndre Renaud2016-06-12-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | This board is based on Snapper 9G45 which has an Atmel AT91SAM9G45 chip and 128MB of SDRAM. It includes a small LCD, 2xUSB host, SD card, Ethernet and two UARTs. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [apply CONFIG_BOOTDELAY transition] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
| * at91: Add driver-model GPIO devices for AT91SAM9G45Simon Glass2016-06-12-0/+18
| | | | | | | | | | | | | | | | | | | | Add these definitions so that GPIOs can be used with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * arm: at91: Add a header file for the real-time clockAndre Renaud2016-06-12-0/+71
| | | | | | | | | | | | | | | | | | | | Add register definitions for the AT91 RTC so that this can potentially be used in U-Boot. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * arm: at91: dts: Bring in device tree file for AT91SAM9G45Simon Glass2016-06-12-0/+1336
| | | | | | | | | | | | | | | | | | | | Add this file from Linux v4.5. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * arm: Allow skipping of low-level init with I-cache onSimon Glass2016-06-12-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling lowlevel_init(). This means that the instruction cache is not enabled and the board runs very slowly. What is really needed in many cases is to skip the call to lowlevel_init() but still perform CP15 init. Add an option to handle this. Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * at91: Add support for the AT91 slow clock controllerAndre Renaud2016-06-12-0/+22
| | | | | | | | | | | | | | | | | | | | This is available on AT91SAM9G45. Add the peripheral address and flag definitions. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: dra7xx: Assign omap_vcores based on board typeKeerthy2016-06-12-78/+0
| | | | | | | | | | | | | | | | | | | | Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-06-12-0/+5
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| * | sunxi: Downclock AHB1 to 100MHz on Allwinner A64Siarhei Siamashka2016-06-10-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test). For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x: 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1 However the FEL mode uses more conservative settings (100MHz for AHB1): 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3190 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0 It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level. Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too). Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-12-80/+91
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| * | arm: mxs: Remove misleading commentsMichael Heimpold2016-06-07-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Both comments look like being copy & paste errors. Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | imx: mx7: implement reset_miscPeng Fan2016-05-31-0/+8
| | | | | | | | | | | | | | | | | | | | | We need to power down lcdif to make 'reset' can pass stress test. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx-common: timer: support i.MX6DQPlusPeng Fan2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | To i.MX6DQPlus, osc can be choosed as the source of gpt, so add i.MX6DQPlus support in gpt_has_clk_source_osc. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx-common: sata: return failure if not i.MX6DQPlusPeng Fan2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The i.MX6DQPlus support sata interface, we should not return failure when CPU is i.MX6DQPlus. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx-common: hab: support i.MX6DQPlusPeng Fan2016-05-24-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support i.MX6DQPlus, otherwise wrong hab address will be used for i.MX6QDPlus. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQPPeng Fan2016-05-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we will get wrong speed grade info i.MX6DQP. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: ddr: support i.MX6D/QPlusPeng Fan2016-05-24-2/+2
| | | | | | | | | | | | | | | | | | | | | Support i.MX6D/QPlus. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx-common: use simpler runtime cpu dection macrosPeng Fan2016-05-24-48/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
| * | imx-common: hab: support i.MX6SOLOPeng Fan2016-05-24-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6SOLO support for hab function. The difference between i.MX6SOLO and i.MX6DL is the number of CPU cores. Besides this, they work the same. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: use simpler runtime cpu dection macrosPeng Fan2016-05-24-36/+29
| | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: support i.MX6SOLO when enable/disable_ldb_di_clock_sourcesPeng Fan2016-05-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support when enable/disable_ldb_di_clock_sources. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx-common: introduce simpler macros for runtime dectionPeng Fan2016-05-24-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Introduce simpler macros for runtime cpu dection. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-05-24-11/+7
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| * | | imx: correct speed grading info for i.MX6ULPeng Fan2016-05-18-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct speed grading info for i.MX6UL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | | armv8: ls2080aqds: Enable QSPI boot supportYuan Yao2016-06-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND bootYuan Yao2016-06-10-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | dts: ls2080aqds: Add QSPI dts nodeYuan Yao2016-06-10-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add QSPI controller and slave dts node for LS2080AQDS board. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | armv8: ls2080aqds: Select QSPI CLK div via SCFGYuan Yao2016-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | board: ls2080a: Add "mcinitcmd" env for MC & DPL deploymentPratiyush Mohan Srivastava2016-06-10-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored (NOR, NAND, SD, SATA, USB) during booting. If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | armv8/ls2080a: configure PMU's PCTBENR to enable WDTYunhui Cui2016-06-10-0/+13
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | siemens,am33x: add draco etamin boardHeiko Schocher2016-06-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the draco CPU board family, etamin is a new variant with bigger flash and more RAM. Due to new flash that uses larger pages (4K) some changes are necessary because it impacts the MTD partition layout and the ubi mount parameters. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Move BOOTDELAY into defconfig, just always be 3 now] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | mtd: nand: omap: allow to switch to BCH16Heiko Schocher2016-06-09-2/+4
| | | | | | | | | | | | | | | | | | | | | support in omap_nand_switch_ecc() also an eccstrength from 16. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | am335x, shc: add support for the am335x based bosch shc boardHeiko Schocher2016-06-09-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06) SHC C3-Sample MPU reference clock runs at 6 MHz Setting MPU clock to 594 MHz Enabling Spread Spectrum of 18 permille for MPU Trying to boot from MMC reading u-boot.img reading u-boot.img U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100) Watchdog enabled I2C: ready DRAM: 512 MiB reloc off 1f783000 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw U-Boot# Signed-off-by: Heiko Schocher <hs@denx.de>
* | | armv7: omap-common: make SPL board_mmc_init() weakHeiko Schocher2016-06-09-1/+1
| | | | | | | | | | | | | | | | | | | | | make this function weak, so board code can setup in SPL MMC init with board special values. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | arm, am335x: Enable Spread Spectrum for the MPUHeiko Schocher2016-06-09-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | Enable Spread Spectrum for the MPU by calculating the required values and setting the registers accordingly. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | am335x: add some missing CM_CLKMODE_DPLL_SSC macrosHeiko Schocher2016-06-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add missing CM_CLKMODE_DPLL_SSC_ACK_MASK, CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and CM_CLKMODE_DPLL_SSC_TYPE_MASK defines. Used for enabling spread spectrum. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm, am335x: add some missing GPIO register definitionsHeiko Schocher2016-06-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | add missing: OMAP_GPIO_IRQSTATUS_SET_0 and OMAP_GPIO_IRQSTATUS_SET_1 registers. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: uniphier: insert dsb barrier to ensure visibility of storeMasahiro Yamada2016-06-09-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: do not overwrite fdt_file environmentMasahiro Yamada2016-06-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This code auto-detects the best-match FDT file name, but it should respect the user's choice if "fdt_file" environment is found in a saved set of environments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: check return code of setenv()Masahiro Yamada2016-06-09-3/+1
| | | | | | | | | | | | | | | | | | Because setenv() may fail, it is better to check its return code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: fix boot mode for PH1-LD11Masahiro Yamada2016-06-09-1/+18
| | | | | | | | | | | | | | | | | | | | | This function is shared between PH1-LD11 and PH1-LD20. The difference is the boot-mode latch for the USB boot mode. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: support eMMC boot for PH1-LD11 and PH1-LD20Masahiro Yamada2016-06-09-3/+154
| | | | | | | | | | | | | | | | | | | | | | | | The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images from an eMMC device. They are useful to reduce the memory footprint of SPL, rather than compiling the whole MMC framework. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | Merge http://git.denx.de/u-boot-samsungTom Rini2016-06-06-19/+452
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
| * | | ARM: exynos: Fix build error if SERIAL is disabled in SPLMarek Vasut2016-05-26-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_SPL_SERIAL_SUPPORT is not defined in include/configs/exynos5-common.h the following error is produced during the build of the SPL: arch/arm/mach-exynos/built-in.o: In function `do_lowlevel_init': ...u-boot/arch/arm/mach-exynos/lowlevel_init.c:221: undefined reference to `debug_uart_init' Add additional condition to check if SPL build is in progress and in that case check if CONFIG_SPL_SERIAL_SUPPORT is also set before enabling the debug UART. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | exynos: video: Convert several boards to driver model for videoSimon Glass2016-05-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update several boards to use driver model for video. This involves changes to the EDP and FIMD (frame buffer) drivers. Existing PWM, simple-panel and pwm-backlight drivers are used. These work without additional configuration since they use the device tree settings in the same way as Linux. Boards converted are: - snow - spring - peach-pit - peach-pi All have been tested. Not converted: - MIPI display driver - s5pc210_universal - smdk5420 - smdk5250 - trats - trats2 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2025-01-01 07:13:36 +0000