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* | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-5/+393
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| * | | kconfig: ls102xa: Change the prompt messagesAlison Wang2014-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR boards, the prompt message "Support ls1021aqds_nor" in Kconfig is not clear. This patch changes it to "Support ls1021aqds". Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls102xa: changing a few targets' configurations.Xiubo Li2014-12-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls1021a: adding a secondary core boot address and kick functionsXiubo Li2014-12-11-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li2014-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: HYP/non-sec: add the pen address BE mode support.Xiubo Li2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang2014-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | kconfig: ls1021a: add SUPPORT_SPLAlison Wang2014-12-11-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: spl: Add I2C linker list in generic .ldsAlison Wang2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: clear EPU registers for deep sleepchenhui zhao2014-12-11-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: fixed a bus frequency setting errorTang Yuantian2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-15/+28
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| * | | | arm: vf610: improve evaluation of reset sourceStefan Agner2014-12-01-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | | | arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)Stefan Roese2014-12-01-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As checkpatch complaines about these camel-case defines, lets change them to only use upper-case characters. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | sata: fix reset_sata for dwc_ahsataSoeren Moch2014-12-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - fix crash when sata device is not initialized - remove disable_sata_clock() since it is not clear which clock for which device should be disabled here - call disable_sata_clock() for mx6 in preboot_os instead Signed-off-by: Soeren Moch <smoch@web.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | | | tbs2910: fix KconfigSoeren Moch2014-12-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix Kconfig for tbs2910 board to prevent crash on relocation Signed-off-by: Soeren Moch <smoch@web.de>
* | | | | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2014-12-10-0/+215
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| * | | | | arm: rmobile: Add mmc.h for sh_mmcif of rmobileNobuhiro Iwamatsu2014-12-10-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver. This adds arch-rmobile/mmc.h that defines mmcif_mmc_init(). Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Add structure for infomation of module control registerNobuhiro Iwamatsu2014-12-05-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The infomation of module control register for R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are almost the same, they can be combined into one structure. This provides structure that summarizes infomation of module control register and default register values. And this structure is the module control use of the kernel at boot time. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Add infomation of bits for module control registerNobuhiro Iwamatsu2014-12-05-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds infomation of bits for module control register. This is used to control modules on ARM R-Car SoCs. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Add mstp_setclrbits and mstp_setclrbits_le32Nobuhiro Iwamatsu2014-12-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This addes macro for set and clear bit control for module control register. This is used when user want to disable the function of the devices corresponding to register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Move control macro of mstp to arch-rmobile/rcar-mstp.hNobuhiro Iwamatsu2014-12-05-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Control macro of mstp is common in R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794). This moves these to arch-rmobile/rcar-mstp.h Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Move module control register to header file of SoCNobuhiro Iwamatsu2014-12-05-0/+39
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Module control registers of R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are same address. This moves these to header file of SoC. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | | | stv0991: enable ethernet supportVikas Manocha2014-12-09-0/+100
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | | | stv0991: Add basic stv0991 architecture supportVikas Manocha2014-12-09-0/+607
| |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stv0991 architecture support added. It contains the support for following blocks - Timer - uart Signed-off-by: Vikas Manocha <vikas.manocha@st.com> [trini: Add arch/arm/cpu/armv7/Makefile hunk] Signed-off-by: Tom Rini <trini@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-12-08-22/+45
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| * | | | arm: am33xx: Handle NAND+I2C boot-device the same way as NANDStefan Roese2014-12-04-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-map NAND&I2C boot-device to the "normal" NAND boot-device. Otherwise the SPL boot IF can't handle this device correctly. Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens Draco leads to this boot-device passed to SPL from the BootROM. With this change, Draco boots just fine into main U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Samuel Egli <samuel.egli@siemens.com>
| * | | | beagle_x15: add board support for Beagle x15Felipe Balbi2014-12-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet. For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap: add support for am57xx devicesFelipe Balbi2014-12-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap_common: expose tps659038 and dra7xx_dpllsFelipe Balbi2014-12-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | expose those two definitions so they can be used by another board which we're adding in upcoming patches. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap5: sdram: mark emif_get_ext_phy_ctrl_const_regs __weakFelipe Balbi2014-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this will allow for boards to overwrite those in case memory setup is different. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap5: make hw_init_data weakFelipe Balbi2014-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this way we can let boards overwrite based on what they need. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap-common: emif: allow to map memory without interleavingFelipe Balbi2014-12-04-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we want to have two sections, one on each EMIF, without interleaving, current code wouldn't enable emif2. Fix that problem. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: dra7xx: prcm: add missing registersFelipe Balbi2014-12-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some boards might want to use USB1 for host, without fiddling those registers it'll be impossible. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap5: tps659038: rename regulator definesFelipe Balbi2014-12-04-10/+10
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-12-08-107/+558
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| * | | | ARM: UniPhier: detect the number of flash banks at run-timeMasahiro Yamada2014-12-09-40/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some UniPhier boards are equipped with an expansion slot that some optional SRAM/NOR-flash cards can be attached to. So, run-time detection of the number of flash banks would be more user-friendly. Until this commit, UniPhier boards have achieved this by (ab)using board_flash_wp_on() because the boot failed if flash_size got zero. Fortunately, this problem was solved by commit 70879a92561a (flash: do not fail even if flash_size is zero). Now it is possible to throw away such a tricky workaround. This commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further refactoring. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: extend register area of init page table for PH1-sLD3Masahiro Yamada2014-12-09-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0x20000000-0x2fffffff: assigned to ARM mpcore (sLD3 only) 0xf0000000-0xffffffff: assigned to Denali NAND controller (sLD3 only) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add device tree sources for PH1-sLD3Masahiro Yamada2014-12-09-0/+186
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add more device nodes to device treeMasahiro Yamada2014-12-09-15/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C controller and NAND controller devices. Fix indentation too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: merge UniPhier config headers into a single fileMasahiro Yamada2014-12-08-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some configurations have been moved to Kconfig and the difference among the config headers of UniPhier SoC variants is getting smaller and smaller. Now is a good time to merge them into a single file. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: move support card select to KconfigMasahiro Yamada2014-12-08-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two kinds of expansion boards which are often used for the UniPhier platform and they are only exclusively selectable. It can be better described by the "choice" menu of Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: move CONFIG_UNIPHIER_SMP to KconfigMasahiro Yamada2014-12-08-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: use boot_is_swapped() macro for readabilityMasahiro Yamada2014-12-08-10/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: remove Denali NAND controller fixup codeMasahiro Yamada2014-12-07-38/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | This ugly work-around code is unnecessary since commit f09eb52b3ffc (mtd: denali: set some registers after nand_scan_ident()). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-10-26 16:29:03 +0000