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* Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2016-07-15-11/+10
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| * mmc: exynos_dw_mmc: remove the unused functionJaehoon Chung2016-07-12-1/+0
| | | | | | | | | | | | | | | | | | | | This function have maintained for supporting Non-FDT. Now, Almost all SoC are changed to fdt style. So there are no that this function is called anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARM: exynos4: dts: add the prefix '/' for aliases nodesJaehoon Chung2016-07-12-10/+10
| | | | | | | | | | | | | | It's correct to use '/' as prefix for aliases nodes. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-07-15-49/+161
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| * | rockchip: sdram: Update the driver to support of-platdataSimon Glass2016-07-14-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for of-platdata with rk3288 SDRAM initr. This requires decoding the of-platdata struct and setting up the device from that. Also the driver needs to be renamed to match the string that of-platdata will search for. The platform data is copied from the of-platdata structure to the one used by the driver. This allows the same code to be used with device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: sdram: Move all DT decoding to ofdata_to_platdata()Simon Glass2016-07-14-38/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Note that only SPL needs to fiddle with the SDRAM registers, so decoding the platform data fully is not necessary in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: syscon: Update to work with of-platdataSimon Glass2016-07-14-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | The syscon devices all end up having diffent driver names with of-platdata, since the driver name comes from the first string in the compatible list. Add separate device declarations for each one, and add a bind method to set up driver_data correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Don't use spl_boot_device() with of-platdataSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | This function cannot look at the device tree when of-platdata is used. Update the code to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Move the MMC setup check earlierSimon Glass2016-07-14-11/+12
| | | | | | | | | | | | | | | | | | | | | When the boot ROM sets up MMC we don't need to do it again. Remove the MMC setup code entirely. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Update the sdram-channel property to support of-platdataSimon Glass2016-07-14-1/+8
| | | | | | | | | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Add a comment to the code to explain the purpose. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | arm: Show cache warnings in U-Boot proper onlySimon Glass2016-07-14-2/+2
| | | | | | | | | | | | | | | | | | Avoid bloating the SPL image size. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | arm: Don't invalidate unaligned cache regionsSimon Glass2016-07-14-21/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present armv7 will unhappily invalidate a cache region and print an error message. Make it skip the operation instead, as it does with other cache operations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
* | | arm: Move check_cache_range() into a common placeSimon Glass2016-07-14-51/+24
| | | | | | | | | | | | | | | | | | | | | This code is common, so move it into a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
* | | ARM: OMAP5+: Enable errata i727Lokesh Vutla2016-07-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Errata i727 is applicable on all OMAP5 and DRA7 variants but enabled only on OMAP5 ES1.0. So, enable it on all platforms. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | stm32: Change USART port to USART6 for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is to remove a halt at about 200KiB while sending a large(1MiB) binary to a micro controller using USART1. USART1 is connected to a PC via an on-board ST-Link debugger that also functions as a USB-Serial converter. However, it seems to loss some data occasionally. So I changed the serial port to USART6 and connected it to the PC using an FTDI USB-Serial cable, therefore the transmission was successfully completed. Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | | stm32: Add SDRAM support for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-1/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SDRAM support for stm32f746 discovery board. This patch depends on previous patch. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | | stm32: clk: Add 200MHz clock configuration for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-1/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds 200MHz clock configuration for stm32f746 discovery board. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | | arm, nds32, sh: remove useless ioremap()/iounmap() definesMasahiro Yamada2016-07-14-34/+0
| | | | | | | | | | | | | | | | | | | | | These defines are valid only when iomem_valid_addr is defined, but I do not see such defines anywhere. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | types.h: move and redefine resource_size_tMasahiro Yamada2016-07-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, this is only defined in arch/arm/include/asm/types.h, so move it to include/linux/types.h to make it available for all architectures. I defined it with phys_addr_t as Linux does. I needed to surround the define with #ifdef __KERNEL__ ... #endif to avoid build errors in tools building. (Host tools should not include <linux/types.h> in the first place, but this is already messy in U-Boot...) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arm: am4x: add U-Boot FIT signing and SPL image post-processingMadan Srinivas2016-07-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the SPL build procedure for AM437x high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed (and optionally encrypted) with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap5: add U-Boot FIT signing and SPL image post-processingAndreas Dannenberg2016-07-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap-common: Update to generate secure U-Boot FIT blobAndreas Dannenberg2016-07-14-14/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds commands so that when a secure device is in use and the SPL is built to load a FIT image (with combined U-Boot binary and various DTBs), these components that get fed into the FIT are all processed to be signed/encrypted/etc. as per the operations performed by the secure-binary-image.sh script of the TI SECDEV package. Furthermore, perform minor comments cleanup to make better use of the available space. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arm: omap-common: secure ROM signature verify APIAndreas Dannenberg2016-07-14-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds an API that verifies a signature attached to an image (binary blob). This API is basically a entry to a secure ROM service provided by the device and accessed via an SMC call, using a particular calling convention. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap-common: add secure rom call API for secure devicesAndreas Dannenberg2016-07-14-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a generic C-callable API for making secure ROM calls on OMAP and OMAP-compatible devices. This API provides the important function of flushing the ROM call arguments to memory from the cache, so that the secure world will have a coherent view of those arguments. Then is simply calls the omap_smc_sec routine. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap-common: add secure smc entryDaniel Allred2016-07-14-9/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an interface for calling secure ROM APIs across a range of OMAP and OMAP compatible high-security (HS) device variants. While at it, also perform minor cleanup/alignment without any change in functionality. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: cache: add missing dummy functions for when dcache disabledDaniel Allred2016-07-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds missing flush_dcache_range and invalidate_dcache_range dummy (empty) placeholder functions to the #else portion of the #ifndef CONFIG_SYS_DCACHE_OFF, where full implementations of these functions are defined. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm64: add better and more generic spin-table supportMasahiro Yamada2016-07-14-4/+134
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two enable methods supported by ARM64 Linux; psci and spin-table. The latter is simpler and helpful for quick SoC bring up. My main motivation for this patch is to improve the spin-table support, which allows us to boot an ARMv8 system without the ARM Trusted Firmware. Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S and the spin-table is supported in a really ad-hoc way, and I see some problems: - We must hard-code CPU_RELEASE_ADDR so that it matches the "cpu-release-addr" property in the DT that comes from the kernel tree. - The Documentation/arm64/booting.txt in Linux requires that the release address must be zero-initialized, but it is not cared by the common code in U-Boot. We must do it in a board function. - There is no systematic way to protect the spin-table code from the kernel. We are supposed to do it in a board specific manner, but it is difficult to predict where the spin-table code will be located after the relocation. So, it also makes difficult to hard-code /memreserve/ in the DT of the kernel. So, here is a patch to solve those problems; the DT is run-time modified to reserve the spin-table code (+ cpu-release-addr). Also, the "cpu-release-addr" property is set to an appropriate address after the relocation, which means we no longer need the hard-coded CPU_RELEASE_ADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Revert "armv8: Enable CPUECTLR.SMPEN for coherency"Tom Rini2016-07-14-8/+0
| | | | | | | | | | | | | | | | | | Upon further review this breaks most other platforms as we need to check what core we're running on before touching it at all. This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-07-11-11/+143
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| * | ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHzVignesh R2016-07-09-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better throughput. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: K2G: Add support for QSPI controllerVignesh R2016-07-09-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has a Cadence QSPI controller to communicate with NOR flash devices. Add DT nodes to support the same. Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor flash slave node for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2g: add support for Davinci SPI controllerVignesh R2016-07-09-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has 4 SPI instances that are compatible with davinci_spi controller(present on previous generation of Keystone2 devices). Add DT nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on SPI-1. Add DT bindings for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2l: Enable Davinci SPI controllerVignesh R2016-07-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2e: Enable Davinci SPI controllerVignesh R2016-07-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2hk: Enable Davinci SPI controllerVignesh R2016-07-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: keystone2: add SPI aliases for davinci SPI nodesVignesh R2016-07-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add aliases for SPI nodes in order for it to be probed by the DM framework. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | | dm: mmc: rockchip: Enable CONFIG_DM_MMC_OPS for all boardsSimon Glass2016-07-11-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable this option to move rockchip over to use driver model for MMC operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | rockchip: Use 'select' instead of defaults in KconfigSimon Glass2016-07-11-27/+10
| |/ |/| | | | | | | | | | | | | Rockchip uses driver model for all subsystems. Specify this in the arm Kconfig rather than as defaults in the Rockchip Kconfig. This means that boards cannot turn these options off, which seems correct. Signed-off-by: Simon Glass <sjg@chromium.org>
* | armv8: Enable CPUECTLR.SMPEN for coherencyMingkai Hu2016-07-08-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm: Fix setjmp (again)Alexander Graf2016-07-08-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp code path with thumv1. Unfortunately it missed a constraint that the adr instruction can only refer to 4 byte aligned offsets. So this patch adds the required alignment hooks to make compilation work again even when setjmp doesn't happen to be 4 byte aligned. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Tom Rini <trini@konsulko.com>
* | video: tegra: Move to using simple-panel and pwm-backlightSimon Glass2016-07-05-72/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have standard drivers for panels and backlights which can do most of the work for us. Move the tegra20 LCD driver over to use those instead of custom code. This patch includes device tree changes for the nvidia boards. I have only been able to test seaboard. If this patch is applied, these boards will also need to be synced with the kernel, and updated to use display-timings: - colibri - medcom-wide - paz00 - tec Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: dts: Sync tegra20 device tree files with LinuxSimon Glass2016-07-05-73/+2154
|/ | | | | | | | Sync everything except the display panel, which will come in a future patch. One USB port is left disabled since we don't want to support it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)Quentin Schulz2016-07-02-1/+350
| | | | | | | | | | | | | | | The Parrot Board is an evaluation board with an Allwinner R16 (assumed to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2 controllable buttons, an LVDS port with separated backlight and capacitive touch panel ports, an audio/microphone jack, a camera CSI port, 2 sets of 22 GPIOs and an accelerometer. The DTS file is identical to the one submitted to the upstream kernel. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add missing boot_media fields in the SPL headerOlliver Schinagl2016-07-02-0/+2
| | | | | | | | | | | Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid code corruption") Added defines for MMC0 and SPI as boot identification. After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected values have been confirmed and added to spl.h Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: uniphier: add external IRQ setup codeMasahiro Yamada2016-07-02-0/+44
| | | | | | | | I will carry this work-around until it is cared in the kernel. This looks up the AIDET node and sets up a register to handle active low interrupt signals. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add AIDET nodesMasahiro Yamada2016-07-02-0/+40
| | | | | | | The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of syscon block related with the interrupt controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: sync Device Trees with upstream LinuxMasahiro Yamada2016-07-02-138/+99
| | | | | | I periodically sync Device Trees for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix typo "talbe"Masahiro Yamada2016-06-30-1/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-28-124/+21
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| * armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIsAbhimanyu Saini2016-06-28-105/+0
| | | | | | | | | | | | | | | | | | | | | | | | Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-10 04:45:56 +0000