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* Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2015-01-30-163/+203
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| * dm: exynos: dts: Set the offset length for cros_ecSimon Glass2015-01-29-0/+1
| | | | | | | | | | | | The EC has no concept of offset, so use a value of 0. Signed-off-by: Simon Glass <sjg@chromium.org>
| * odroid u3: dts: add missing i2c aliasesPrzemyslaw Marczak2015-01-29-0/+7
| | | | | | | | | | | | | | | | This change fixes i2c bus numbering for Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * exynos5: pinmux: check flag for i2c configPrzemyslaw Marczak2015-01-29-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | Some versions of Exynos5 supports High-Speed I2C, on few interfaces, this change allows support this. The new flag is: PINMUX_FLAG_HS_MODE Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * arndale: dts: add missing i2c aliasesPrzemyslaw Marczak2015-01-29-0/+8
| | | | | | | | | | | | | | | | | | | | Without this alias setting, the seq numbers of the i2c devices are wrong. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * exynos4: dts: add missing i2c propertiesPrzemyslaw Marczak2015-01-29-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch modify i2c nodes in exynos4.dtsi with: - adding proper interrupts arrays for each i2c node, which allows to decode periph id - add reg address for each i2c node for i2c driver internal use Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * dm: i2c: Provide an offset length parameter where neededSimon Glass2015-01-29-1/+1
| | | | | | | | | | | | | | | | | | | | Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: exynos: dts: Use GPIO bank phandles for GPIOsSimon Glass2015-01-29-39/+30
| | | | | | | | | | | | | | | | U-Boot now supports using GPIOs using bank phandles instead of global numbers. Update the exynos device tree files to use this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOsSimon Glass2015-01-29-85/+109
| | | | | | | | | | | | This new method is much easier and matches the kernel. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: mmc: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-3/+4
| | | | | | | | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: zynq: Remove inline gpio functionsSimon Glass2015-01-29-15/+0
| | | | | | | | | | | | | | These functions serve no useful purpose, and conflict with the generic API. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: tegra: video: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-4/+5
| | | | | | | | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: armv7 fix spelling of SCTRLPeng Fan2015-01-30-4/+4
| | | | | | | | | | | | | | SCTLR is the abbreviation of System Control Register, so we should use SCTLR but not SCTRL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | vexpress64: support the Juno Development PlatformLinus Walleij2015-01-30-0/+4
| | | | | | | | | | | | | | | | | | | | The Juno Development Platform is a physical Versatile Express device with some differences from the emulated semihosting models. The main difference is that the system is split in a SoC and an FPGA where the SoC hosts the serial ports at totally different adresses. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | vexpress64: get rid of CONFIG_SYS_EXTRA_OPTIONSLinus Walleij2015-01-30-1/+13
|/ | | | | | | | | | | | | | | | | | | | The Versatile Express ARMv8 semihosted FVP platform is still using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure some compile-time flags. Get rid of this and create a Kconfig entry for the FVP model, and a selectable bool for the semihosting library. The FVP subboard is now modeled as a target choice so we can eventually choose between different ARMv8 versatile express boards (FVP, base model, Juno...) this way. All dependent symbols are updated to reflect this. The 64bit Versatile Express board symbols are renamed VEXPRESS64 so we have some chance to see what is actually going on. Tested on the FVP fast model. Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-1/+21
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| * ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * ARM: atmel: sama5d4: add usb platform dataBo Shen2015-01-19-1/+1
| | | | | | | | | | | | The SAMA5D4 has the same usb platform data with SAMA5D3 SoC. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-26-5/+51
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| * | ARM: zynq: List qspi, smc and nand baseaddressesMichal Simek2015-01-26-0/+3
| | | | | | | | | | | | | | | | | | Add missing addresses to the list. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: List nand, qspi and jtag boot modesMichal Simek2015-01-26-0/+11
| | | | | | | | | | | | | | | | | | Use full boot mode list in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: slcr: Dont modify the reserved bitsSiva Durga Prasad Paladugu2015-01-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: ddrc: Setup half of memory only for ECC caseMichal Simek2015-01-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup half of memory from ram_size for ECC case. All the time the same board can be configured with or without ECC. Based on ECC case detection use half of memory with the same configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Remove empty lineMichal Simek2015-01-26-1/+0
| | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Enable the Neon instructionsMichal Simek2015-01-26-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the lowlevel_init to enable the Neon instructions. Initially the u-boot was causing undefined instruction exception if loaded through tcl, and working fine if loaded through FSBL. The exception was causing in convertion formula of given time to ticks. It was because, the Neon instructions were disabled and hence causing the undefined exception. In FSBL case, the FSBL was enabling the Neon instructions. Hence, added the lowlevel_init to enable the Neon instructions. Also enable neon instructions for non-xilinx toolchain. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-marvellTom Rini2015-01-25-3/+8
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| * | | ARM: kirkwood: fix cpu info for 6282 device idLuka Perkov2015-01-25-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Luka Perkov <luka@openwrt.org> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Stefan Roese <sr@denx.de>
* | | | fsl/ls1021qds: Add deep sleep supporttang yuantian2015-01-24-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD bootAlison Wang2015-01-23-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | arm: ls102xa: Update snoop settings for CCI-400Alison Wang2015-01-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. These CCI-400 operations are moved to board_early_init_f() to be initialized earlier. For S4 slave interface, issuing of snoop requests and DVM message requests are enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ARM: HYP/non-sec: Make variable gic_dist_addr as a local onetang yuantian2015-01-23-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defining variable gic_dist_addr as a globe one prevents some functions, which use it, from being used before relocation which is the case in the deep sleep resume process on Freescale SoC platforms. Besides, we can always get the GIC base address by calling get_gicd_base_address() without referring gic_dist_addr. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | crypto/fsl: Add fixup for crypto nodeRuchika Gupta2015-01-23-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Fix commit message indentation] Reviewed-by: York Sun <yorksun@freescale.com>
* | | | arm: ls102xa: Add dummy gpio.h to enable CONFIG_OF_CONTROLRuchika Gupta2015-01-23-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. As a result, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. The right fix would be to split the lib/fdtdec.c to remove dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL for LS102x platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as defaultAlison Wang2015-01-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will be used via hwconfig. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | arm/ls1021a: Add workaround for DDR erratum A008378York Sun2015-01-23-0/+1
|/ / / | | | | | | | | | | | | | | | | | | Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-01-23-157/+620
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| * | | sunxi: Hookup OTG USB controller supportHans de Goede2015-01-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hookup OTG USB controller support and enable the otg controller + USB-keyb on various tablets. This allows tablet owners to interact with u-boot without needing to solder a serial console onto their tablet PCB. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: video: Use frontend for dma on sun4i to fix memory bandwidth problemsHans de Goede2015-01-22-0/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing has shown that on sun4i the display backend engine does not have deep enough fifo-s causing flickering / tearing in full-hd mode due to fifo underruns. On sun4i use the display frontend engine to do the dma from memory, as the frontend does have deep enough fifo-s. As added advantage of this is that it results in much better memory bandwidth as it reduces the amount of dram bank switches, for more details see: http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html Note that this changes the pipeline searched for in the simplefb node, we can get away with doing this now, since no kernel has yet shipped with simplefb dtb nodes, and I will make sure to get a simplefb node with the new pipeline into 3.19 before it ships. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Stop differentiating between 512M and 1G variants of the same boardHans de Goede2015-01-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While working on adding more boards I noticed that we lack a config for the 512M cubieboard, and that some of the new boards which I want to add also have 512M and 1G variants, rather then adding 2 defconfig's for all of these, lets switch the exising boards which have both a 512M and 1024M variant over to the sun4i dram autoconfig code. This also drops the foo_RAMSIZE_defconfig variants of boards where we currently have 2 separate configs already. Note: 1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with a value other then its default for now, but we need this to be configurable to support some new boards with auto dram config. 2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match the defaults, this is done to make it more clear what values are used for a certain board. This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G variants, the dram autoconfig code has also been tested on a 512M mk802 (a defconfig for the mk802 is added in a later patch). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: mmc: Add support for sun9i (A80)Hans de Goede2015-01-22-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks on the A80 are hooked up slightly different, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun9i: Add sun9i (A80) clock setup supportHans de Goede2015-01-22-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial sun9i (A80) clock setup support, enough to get the uart + mmc going. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun9i: Add clock_sun9i.h with ccu register layout for sun9iHans de Goede2015-01-22-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a headerfile with the sun9i ccu register layout. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun9i: Add cpu_sun9i.h with iomem definesHans de Goede2015-01-22-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a headerfile with all the base addresses from the sun9i blocks. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Rename cpu.h to cpu_sun4i.hHans de Goede2015-01-22-145/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite different, so add a wrapper cpu.h which includes the right mach specific cpu_sun#i.h based on mach, like we already do with clock.h and dram.h . Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headersHans de Goede2015-01-22-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Which pll-s are available depends on the machine type, move the clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files so that we only declare what is actually available. e.g. clock_get_pll5p() is not available on sun6i / sun8i, and with sun9i we get a completely different set of plls. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Drop pll6 setting from clock_init_uartHans de Goede2015-01-22-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the comment says now that we have SPL support this is no longer necessary, as PLL6 is already setup with the exact same parameters by the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: display: Make lcd display clk phase configurableHans de Goede2015-01-22-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup. This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value. This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit. The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-01-22-1126/+128
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| * | | | ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2Masahiro Yamada2015-01-23-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-sLD3, PH1-LD6b have DDR channel 2. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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