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* ARM: dts: keystone2: Do not use LPAE addresses in U-BootLokesh Vutla2015-10-22-9/+8
| | | | | | | | Keystone dts files assumes that LPAE is enabled and top level root node uses 64bit addresses. This breaks the keystone boot with CONFIG_OF_CONTROL enabled. So do not use 64 bit addresse in U-Boot DT. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: dts: Keystone2: Import generic dt files from Linux KernelLokesh Vutla2015-10-22-0/+738
| | | | | | | Import various generic dts files from Linux kernel so that all keystone2 platforms can be DT in U-boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Fix serial port initLokesh Vutla2015-10-22-0/+2
| | | | | | | | With CONFIG_DM_SERIAL is enabled NS16550_init() cannot be called directly. Driver probe should be taking care of this. So call this function only when DM_SERIAL is not enabled. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* omap-common: Common get_board_serial function to pass serial through ATAGPaul Kocialkowski2015-10-22-0/+19
| | | | | | | | | Since there is a common function to grab the serial number from the die id bits, it makes sense have one to parse that serial number and feed it to the serial ATAG. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common function to display die id, replacing omap3-specific versionPaul Kocialkowski2015-10-22-24/+12
| | | | | | | | | This introduces omap_die_id_display to display the full die id. There is no need to store it in an environment variable, that no boot script is using anyway. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common serial and usbethaddr functions based on die idPaul Kocialkowski2015-10-22-24/+30
| | | | | | | | | Now that we have a common prototype to grab the omap die id, functions to figure out a serial number and usb ethernet address can use it directly. Those also get an omap_die_id prefix for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap5: omap_die_id supportPaul Kocialkowski2015-10-22-0/+12
| | | | | | | | This introduces omap5 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap4: omap_die_id supportPaul Kocialkowski2015-10-22-5/+12
| | | | | | | | This introduces omap4 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: omap_die_id supportPaul Kocialkowski2015-10-22-10/+6
| | | | | | | | This replaces the previous get_dieid definition with omap_die_id, that matches the common omap_die_id definition. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common omap_die_id definitionPaul Kocialkowski2015-10-22-0/+7
| | | | | | | | This introduces a common definition for omap_die_id, that aims at providing a common interface for accessing omap platform's die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-marvellTom Rini2015-10-20-28/+3357
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| * arm: mvebu: Enable DM_SERIAL on AXP / A38x boardsStefan Roese2015-10-21-0/+1
| | | | | | | | | | | | | | | | This patch enables DM_SERIAL for all ARCH_MVEBU boards (AXP & A38x). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * arm: mvebu: Add DM (driver model) supportStefan Roese2015-10-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver model support for some Marvell MVEBU SoC's. Including Armada XP and 38x. All 3 currently mainlined boards are converted. DM is now selected automatically for MVEBU platforms. With this DM support now available for MVEBU, hardcoding the base addresses and other information is not necessary any more. Probing should be done by using the values provided via the device tree now instead. For this the driver also need to be converted to DM. Patches for some of the drivers will follow. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * arm: mvebu: Add basic Armada XP / 38x dtsi/dts filesStefan Roese2015-10-21-0/+3257
| | | | | | | | | | | | | | | | | | | | These will be needed by the upcoming DM (driver model) support for the Armada XP / 38x SoC's. This will provide DT based probing. The dts files are copied 1:1 from the Linux kernel release v4.2. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * arm: mvebu: Do not call board_init_r() from board_init_f()Stefan Roese2015-10-21-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of calling board_init_r() directly from board_init_f(), just return from board_init_f(). This will make the code continue executing in crt0.S _main(), from which the board_init_r() is called. This patch aligns the MVEBU SPL with the correct SPL design as well as reduces the stack utilisation slightly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPLStefan Roese2015-10-21-12/+19
| | | | | | | | | | | | | | | | | | When running on the AXP I sometimes noticed a strange behavior. As some characters are not echoed on the U-Boot prompt. Not disabling the lowlevel_init code, especially calling cpu_init_cp15() in the main U-Boot seems to solve this issue. Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: Add option to use UART xmodem protocol via kwbootStefan Roese2015-10-21-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the use of the kwboot tool, to boot mainline U-Boot on the Marvell Armada XP/38x SoC's. This is done by returning to the SoC's BootROM after SPL has initialized the SDRAM. We need to make sure to not reconfigure the internal register space and MBARs. Otherwise the BootROM will not be able to continue after SPL jumps back to it. To use this feature, please don't forget to change the BOOT_FROM line in your board specfic kwbimage.cfg file this way: BOOT_FROM uart Tested on these Marvell eval boards: DB-MV784MP-GP - Armada XP DB-88F6820-GP - Armada 38x Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * arm: mvebu: Move Armada XP/38x Kconfig to mach specific Kconfig fileStefan Roese2015-10-20-12/+25
| | | | | | | | | | | | Introduce a mach-mvebu/Kconfig for all Armada based SoC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | sunxi: Add CHIP supportMaxime Ripard2015-10-20-1/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack and two connectors to plug additional boards on top of it. The DT is identical to the DT submitted to the upstream kernel. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | axp209: Sync the DTSI with the kernelMaxime Ripard2015-10-20-0/+5
| | | | | | | | | | | | | | | | Linux had a number of changes to the AXP209 DTSI. Sync ours. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun5i: Sync the DTSI with the kernelMaxime Ripard2015-10-20-10/+146
| | | | | | | | | | | | | | | | Add the latest kernel changes to the sun5i family DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: board: Only try to use the MMC related functions if enabledMaxime Ripard2015-10-20-1/+5
| | | | | | | | | | | | | | | | | | | | | | So far, even if CONFIG_MMC was not enabled the board code was trying to use the MMC-related functions, resulting in linker errors. Protect those calls by an ifdef. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add defconfig for the Sinovoip BPI-M2 boardHans de Goede2015-10-20-1/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features 1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver, stereo headphone jack and hdmi video output. The dts changes are identical to the dts files submitted upstream. A few notes on the use if dldo and aldo regulators. DLDO1 is used for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet phy. ALDO1 is used to power the sdio wifi module. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: power: Unify axp pmic function namesHans de Goede2015-10-20-11/+2
| | | | | | | | | | | | | | | | | | Stop prefixing the axp functions for setting voltages, etc. with the model number, there ever is only one pmic driver built into u-boot, this allows simplifying the callers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Remove board defconfig-s for specific Q8 tablet PCB-sHans de Goede2015-10-20-475/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with an A13 / A23 / A33 SoC, there is no need for these PCB variant specific defconfig-s and they only serve to confuse the user. Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig for A13 based Q8 tablets there is not even a dts file for these in the upstream kernel, which is all the more reason to remove them. The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6, Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig. This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs but there is no reason to assume that it will not work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Switch to using malloc_simple for the splHans de Goede2015-10-20-0/+2
| | | | | | | | | | | | | | | | | | | | common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes, and .data from 0x54c to 0x144 bytes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sunxi: Enable CONFIG_SPL_STACK_RHans de Goede2015-10-20-0/+1
|/ | | | | | | | | | | | Select CONFIG_SPL_STACK_R for sunxi boards, this gives us much more room on the stack once we've the DRAM running. Besides being a good change to have on itself, this also paves the way for switching to using malloc_simple in the SPL which cuts of close to 4KiB of the SPL size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-10-19-0/+1
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| * ARM: rpi: add another revision of Raspberry Pi A+Lubomir Rintel2015-10-19-0/+1
| | | | | | | | | | | | | | | | Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1, (C) Raspberry Pi 2014". A standard A+ board, much like the one with version 0x12, didn't notice any differencies. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
* | ARM: k2e/l: Apply WA for selecting PA clock sourceLokesh Vutla2015-10-17-3/+8
|/ | | | | | | | | | | | | | | On keystone2 Lamarr and Edison platforms, the PA clocksource mux in PLL REG1, can be changed only after enabling its clock domain. So selecting the output of PASS PLL as input to PA only after enabling the clockdomain. This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>" and based on the previous work done by "Hao Zhang <hzhang@ti.com>" Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code") Reported-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-10-16-0/+17
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| * arm: dts: socfpga: add "u-boot,dm-pre-reloc" to socfpga_cyclone5_socdk dtsDinh Nguyen2015-10-17-0/+3
| | | | | | | | | | | | | | We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in order for the SPL to use SD/MMC. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: enable data/inst prefetch and shared override in the L2Dinh Nguyen2015-10-17-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: mmu: Add missing volatile for reading SCTLR registerAlison Wang2015-10-16-1/+1
|/ | | | | | | | | | | | | Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-10-15-27/+55
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| * armv8/gic: Fix GIC v2 initializationThierry Reding2015-10-15-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot. Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * armv8/mmu: Set bits marked RES1 in TCRThierry Reding2015-10-15-3/+7
| | | | | | | | | | | | | | | | | | | | | | For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * armv8/mmu: Clean up TCR programmingThierry Reding2015-10-15-2/+2
| | | | | | | | | | | | | | | | | | Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2015-10-14-4625/+11991
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| * | arm: armv8 correct value passed to __asm_dcache_allPeng Fan2015-09-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * | arm: Correct comments in crt0.S for the recent SPL improvementsSimon Glass2015-09-12-20/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current comments need a bit of tweaking since we now support stack and global_data relocation in SPL. Also add a reference to the README. For AArch64 this is not implemented, so leave a TODO for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tim Harvey <tharvey@gateworks.com>
* | | pci: pcie_imx: Fix hang on mx6qpFabio Estevam2015-10-15-0/+2
| |/ |/| | | | | | | | | | | | | | | | | | | PCI driver currently hangs on mx6qp. Toggle the reset bit with the appropriate timings to fix the issue. Based on the FSL kernel driver implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | ls102xa: Fix reset hangFabio Estevam2015-10-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 623d96e89aca6("imx: wdog: correct wcr register settings") issuing a 'reset' command causes the system to hang. Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian. This means that the watchdog on LS1021 has been working by accident as it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c. Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only revelead the endianness problem on LS102x. In order to fix the reset hang, introduce a reset_cpu() implementation that is specific for ls102x, which accesses the watchdog WCR register in big-endian format. All that is required to reset LS102x is to clear the SRS bit. This approach is a temporary workaround to avoid a regression for LS102x in the 2015.10 release. The proper fix is to make the watchdog driver endian-aware, so that it can work for i.MX, Vybrid and LS102x. Reported-by: Sinan Akman <sinan@writeme.com> Tested-by: Sinan Akman <sinan@writeme.com> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | lpc32xx: fix calculation of HCLK PLL output clockVladimir Zapolskiy2015-10-11-5/+5
| | | | | | | | | | | | | | | | Execution branches on feedback mode are swapped, this has no effect if default direct mode is on (then p_div is equal to 1 and Fout equals to Fcco), that's why the problem remained unnoticed for a long time. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN configVladimir Zapolskiy2015-10-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to ARM PrimeCell PL175 documentation WAIT_OEN config value is defined without any additional clocks added to the value set by a client, the change fixes the wrong interface to WAIT_OEN config. The change also touches a single user of LPC32xx EMC and corrects configured "output enable delay" value on its side according to the changed interface. No functional change intended. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | arndale: Apply Cortex-A15 errata #773022 and #774769Ian Campbell2015-10-11-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We run 4 Arndale boards in our automated test framework, they have been running quite happily for quite some time using a Debian Wheezy userspace. However when upgrading to a Debian Jessie we started seeing frequent segmentation faults from gcc when building the kernel, to the extent that it is unable to successfully build the kernel twice in a row, and often fails on the first attempt. Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417 which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html and CPU Errata 773022 and 774769. This errata needs to be applied to all processors in an SMP system, meaning that the usual strategy of applying them in arch/arm/cpu/armv7/start.S is not appropriate (since that applies to the boot processor only). Instead we apply these errata in the secure monitor which is code that is traversed by all processors as they are brought up. The net affect on Arndale is that ACTLR changes from 0x40 to 0x2000042. I ran 17 kernel compile iterations overnight with no segfaults. Runtime testing was done on our v2014.10 based branch and forward ported (with only minimal and trivial contextual conflicts) to current master, where it has been build tested only. I suppose in theory these errata apply to any Exynos5250 based boards, but Arndale is the only one I have access to and I have therefore chosen to be conservative and only apply it there. Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list numerically sorted. Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
* | vexpress64: fvp dram: add DRAM configurationRyan Harkin2015-10-11-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create an additional FVP configuration to boot images pre-loaded into DRAM. Sometimes it's preferential to boot the model by loading the files directly into DRAM via model parameters, rather than using SemiHosting. An example of model parmaters that are used to pre-load the files into DRAM: --data cluster0.cpu0=Image@0x80080000 \ --data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \ --data cluster0.cpu0=uInitrd@0x84000000 Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [trini: Update board/armltd/vexpress64/Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
* | dm: dts: ls1021a-twr: Enable DSPI2 on LS1021ATWRYuan Yao2015-10-11-0/+16
| | | | | | | | | | | | | | | | | | Erratum A-008022 has been fixed on LS1021A Rev2.0. So we can use DSPI2 now, this patch enable DSPI2 in dts for LS1021ATWR. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | rockchip: Reconfigure the malloc based to point to system memorySjoerd Simons2015-10-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When malloc_base initially gets setup in the SPL it is based on the current (early) stack pointer, which for rockchip is pointing into SRAM. This means simple memory allocations happen in SRAM space, which is somewhat unfortunate. Specifically a bounce buffer for the mmc allocated in SRAM space seems to cause the mmc engine to stall/fail causing timeouts and a failure to load the main u-boot image. To resolve this, reconfigure the malloc_base to start at the relocated stack pointer after DRAM has been setup. For reference, things did work fine on rockchip before 596380db was merged to fix memalign_simple due to a combination of rockchip SDRAM starting at address 0 and the dw_mmc driver not checking errors from bounce_buffer_start. As a result, when a bounce buffer needed to be allocated mem_align simple would fail and return NULL. The mmc driver ignored the error and happily continued with the bounce buffer address being set to 0, which just happened to work fine.. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini2015-10-03-6/+8
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