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| * | | | ARM: UniPhier: add DDR PHY training codeMasahiro Yamada2014-12-30-3/+586
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | This training code provides run-time adjustment of DDR PHY parameters for stable DDR operation. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2014-12-30-9/+57
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| * | | arm: exynos: clock: support SPLL as mmc source clock for exynos5420Joonyoung Shim2014-12-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC of exynos5420 can select SPLL as source clock, so add to support SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | odroid-XU3: Add entry for DTS EHCI GPIOSjoerd Simons2014-12-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add samsung,vbus-gpio information for the XU3. This allows the usage of the EHCI controller on the XU3, which is connected to the SMSC LAN9514 chip (usb hub + network). Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | exynos5420: fix compilation without parade videoSjoerd Simons2014-12-22-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all exynos 5420 based devices with an LCD also have a parade LVDS bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled and CONFIG_VIDEO_PARADE is not. As a side-effect move the parade functions from the exynos system header file to its own file. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Exynos5800: The Peach-Pi board does not have a Parade video bridgeSjoerd Simons2014-12-22-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the Pi. So drop it from device-tree Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang2014-12-22-1/+51
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | bcm281xx: add support for "USB OTG clock"Steve Rae2014-12-29-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
* | | ARM: rpi: support model A+Stephen Warren2014-12-29-0/+1
| | | | | | | | | | | | | | | | | | | | | Add a board rev entry for the new model A+, and augment the board rev error handling code to be a bit more verbose. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | arm: semihosting: get rid of forward declarationsLinus Walleij2014-12-29-89/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By rearranging the functions in the semihosting code we can avoid forward-declaration of the internal static functions. This puts the stuff in a logical order: read/open/close/len and then higher-order functions follow at the end. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | arm: semihosting: fix up compile bugsLinus Walleij2014-12-29-50/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is currently a regression when using newer ARM64 compilers for semihosting: the way long types are inferred from context is no longer the same. The semihosting runtime uses long and size_t, so use this explicitly in the semihosting code and interface, and voila: the code now works again. Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Suggested-by: Mark Hambleton <mark.hambleton@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | arm: semihosting: staticize internal functionsLinus Walleij2014-12-29-8/+9
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semihosting code exposes internal file handle handling functions to read(), open(), close() and get the length of a certain file handle. However the code using it is only interested in either reading and entire named file into memory or getting the file length of a file referred by name. No file handles are used. Thus make the file handle code internal to this file by removing these functions from the semihosting header file and staticize them. This gives us some freedom to rearrange the semihosting code without affecting the external interface. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: UniPhier: select CONFIG_SPLMasahiro Yamada2014-12-18-0/+1
| | | | | | | | | | | | Now UniPhier platform is only supported with SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada2014-12-18-4/+0
| | | | | | | | | | | | init_page_table is only set on SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: fix property names of aliases nodes of device treesMasahiro Yamada2014-12-18-15/+15
|/ | | | | | | The property name of the "aliases" node should be "serial*" to assign a desired number for the device sequence number. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-43/+78
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| * socfpga: correctly increment freeze_controller_base addressDinh Nguyen2014-12-06-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * socfpga: add missing struct member fifo_triple_byteDinh Nguyen2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | socfpga_scan_manager structure was missing a data member. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.hStefan Roese2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bitsStefan Roese2014-12-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probingStefan Roese2014-12-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devicesStefan Roese2014-12-06-0/+28
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * arm: socfpga: dts: Add spi0 alias for Cadence QSPI driverStefan Roese2014-12-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsiStefan Roese2014-12-06-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * arm: socfpga: dts: Move to SPDX license identifiersStefan Roese2014-12-06-36/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The socfpga dts files are copied from the Rocketboards.org repository. In U-Boot we usually replace the full-blown license header text with the SPDX license identifiers. Lets do this for these new dts files as well. I just forgot to do this while adding the DT support for socfpga. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-7/+616
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| * | dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | ARM: tegra: Add support for nyan-big boardAllen Martin2014-12-11-0/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here. The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> (rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
| * | tegra: dts: Sync tegra124.dtsi with linux kernelSimon Glass2014-12-11-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings for pinctrl. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | dts: Bring in Chrome OS keyboard device tree definitionSimon Glass2014-12-11-0/+105
| | | | | | | | | | | | | | | | | | | | | This will be used by nyan-big, but bring it in in a separate patch since it will be common to other boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-0/+5
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | imx:mx6slevk add board level support for usbPeng Fan2014-11-14-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-5/+393
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| * | | kconfig: ls102xa: Change the prompt messagesAlison Wang2014-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR boards, the prompt message "Support ls1021aqds_nor" in Kconfig is not clear. This patch changes it to "Support ls1021aqds". Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls102xa: changing a few targets' configurations.Xiubo Li2014-12-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls1021a: adding a secondary core boot address and kick functionsXiubo Li2014-12-11-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li2014-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: HYP/non-sec: add the pen address BE mode support.Xiubo Li2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang2014-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | kconfig: ls1021a: add SUPPORT_SPLAlison Wang2014-12-11-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: spl: Add I2C linker list in generic .ldsAlison Wang2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: clear EPU registers for deep sleepchenhui zhao2014-12-11-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: fixed a bus frequency setting errorTang Yuantian2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-15/+28
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| * | | | arm: vf610: improve evaluation of reset sourceStefan Agner2014-12-01-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7. Signed-off-by: Stefan Agner <stefan@agner.ch>
generated by cgit v1.1 at 2024-10-25 14:32:27 +0000