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* | ARM64: zynqmp: Use 64bit size cell format for main amba busMichal Simek2016-11-15-65/+65
| | | | | | | | | | | | | | Use 64bit size cell for main amba bus instead of 32bit because PCIe node requires it Change 64bit sizes also for all others IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add ocm node in dtsiNaga Sureshkumar Relli2016-11-15-0/+7
| | | | | | | | | | | | | | | | This patch adds ocm controller node in zynqmp.dtsi. needed for OCM edac support. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add device tree properties for ZynqMP GT coreAnurag Kumar Vulisha2016-11-15-0/+23
| | | | | | | | | | | | | | | | | | This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Revert "ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes"Michal Simek2016-11-15-2/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit bd750e7a6c515c081b72d4ef108a2bfa691a3fd1 Implemented the new workaround for auto tuning based on zynqmp compatible string, so removed the 'broken-tuning' property. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: change sdhci compatible string.Sai Krishna Potthuri2016-11-15-2/+9
| | | | | | | | | | | | | | | | This patch changes the compatible string for sdhci node, adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node. Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: List all SMMU idsMichal Simek2016-11-15-1/+72
| | | | | | | | | | | | Add SMMU description for all tested IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for zynqmp fpga managerNava kishore Manne2016-11-15-0/+4
| | | | | | | | | | | | | | Add support for zynqmp fpga manager. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add cortexa53 edac nodeNaga Sureshkumar Relli2016-11-15-0/+4
| | | | | | | | | | | | | | | | This patch adds edac node for arm cortexa53 to report errors on L1 and L2 caches. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Revert "ARM64: zynqmp: Add serdes address space dp driver"Michal Simek2016-11-15-2/+1
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 786db82bd5bf09cc8f78c8b14445e843d7566b1c. Since we are using serdes driver , no need of mapping serdes register space into DP driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: drm: Add DMA indexHyun Kwon2016-11-15-3/+5
| | | | | | | | | | | | | | | | Each plane can be associated with multiple DMA channels. So add index for each DMA channel. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Sync gpio node propertiesMichal Simek2016-11-15-2/+2
| | | | | | | | | | | | Keep dtsi in sync with mainline kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove xlnx,id propertyMichal Simek2016-11-15-16/+0
| | | | | | | | | | | | | | Remove unused xlnx,id property because it is not the part of DT binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: pci: Updating device tree as per upstreamBharat Kumar Gogada2016-11-15-1/+4
| | | | | | | | | | | | | | | | Updating required device tree changes as per mainlined driver from 4.6 kernel. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Support for multiple PM IDs assigned to a PM domainFilip Drazic2016-11-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, it was assumed that there is a 1:1 mapping between PM ID defined in the platform firmware and a PM domain. However, there can be a situation where multiple PM IDs belong to a single PM domain (e.g. PM IDs for GPU and two pixel processors correspond to a single PM domain). This patch adds support for assigning more than one PM ID to a single PM domain. Updated documentation accordingly. Assigned pixel processors PM IDs to GPU PM domain. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Add PM domains for GPU and PCIEFilip Drazic2016-11-15-0/+12
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused PM domains for PLLFilip Drazic2016-11-15-25/+0
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused DDR PM domainFilip Drazic2016-11-15-5/+0
| | | | | | | | | | | | | | | | | | | | DDR power states are handled by the PM firmware, so this domain is redundant. Also, since there is no device using this PM domain, it will be powered off during boot, which is wrong. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove note about level shifter on zcu102Michal Simek2016-11-15-1/+1
| | | | | | | | | | | | i2c device is just level shifter. Remove reference from dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add dcc port to dtsiMichal Simek2016-11-15-0/+11
| | | | | | | | | | | | | | | | Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add gpio-keys for zcu102Michal Simek2016-11-15-0/+15
| | | | | | | | | | | | | | There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102Michal Simek2016-11-15-0/+9
| | | | | | | | | | | | Show user that Linux is alive on the board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable can1 for ep108Naga Sureshkumar Relli2016-11-15-0/+8
| | | | | | | | | | | | | | | | This patch enables can1 for ep108. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Added clocks to DT for ep108VNSL Durga2016-11-15-0/+44
| | | | | | | | | | | | | | Added clks for ep108 platform. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana2016-11-15-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Zynqmp DMA driver expects two clocks (main clock and apb clock) LPDDMA clock cofiguration is missing for the same in the zynqmp-clk.dtsi file. This patch updates for the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Fix secondary bootmode enablingMichal Simek2016-11-15-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for SD1 with level shifters bootmodeSiva Durga Prasad Paladugu2016-11-15-0/+1
| | | | | | | | | | | | | | Add support for SD1 with level shifters bootmode. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: nand: Runtime detection of nand buswidth through slcrMichal Simek2016-11-15-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to check the buswidth on nand flash at runtime based on nand MIO configurations done by FSBL. User needs to correctly configure the MIO's based on the buswidth supported by the nand flash which is present on the board. Added nand8 and nand16 @periph names on slcr driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Add support for the topic-miami system-on-modules and carrier boardsMike Looijmans2016-11-15-0/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Make SYS_VENDOR configurableMike Looijmans2016-11-15-0/+1
| | | | | | | | | | | | | | | | Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | tools: mkimage: Add support for initialization table for Zynq and ZynqMPMike Looijmans2016-11-15-0/+14
|/ | | | | | | | | | | | | | | | | | The Zynq/ZynqMP boot.bin file contains a region for register initialization data. Filling in proper values in this table can reduce boot time (e.g. about 50ms faster on QSPI boot) and also reduce the size of the SPL binary. The table is a simple text file with register+data on each line. Other lines are simply skipped. The file can be passed to mkimage using the "-R" parameter. It is recommended to add reg init file to board folder. For example: CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: dts: dra7xx: Update spi-max-frequency for qspi slave nodeVignesh R2016-11-13-2/+2
| | | | | | | | | Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: keystone2: PLL: Enable glitch free initialization sequenceLokesh Vutla2016-11-13-8/+8
| | | | | | | | | | Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy2016-11-13-1/+6
| | | | | | | | | | | | | | | | | While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: print the cache config option in hex instead of decimalKeerthy2016-11-13-1/+1
| | | | | | | Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-11-08-32/+69
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| * ARM: tegra186: call secure monitor for all cache-wide opsStephen Warren2016-11-07-3/+21
| | | | | | | | | | | | | | | | | | An SMC call is required for all cache-wide operations on Tegra186. This patch implements the two missing hooks now that U-Boot supports them, and fixes the mapping of "hook name" to SMC call code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * armv8: add hooks for all cache-wide operationsStephen Warren2016-11-07-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: translate __asm_flush_l3_cache to assemblyStephen Warren2016-11-07-23/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When performing a cache disable function, code must not access DRAM. That is because when the cache is disabled, it will be bypassed and all loads and stores will be serviced by RAM. This prevents accessing any dirty data in the cache. In turn, this means the stack cannot be used, since that is in RAM. To guarantee that code doesn't use RAM (and in particular the stack) __asm_flush_l3_cache() must be manually implemented in assembly, rather than implemented in C since the compiler won't know not to touch RAM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: ensure nvtboot_boot_x0 alignmentStephen Warren2016-11-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | nvtboot_boot_x0 is a 64-bit variable and hence must be 64-bit aligned. So far this has happened by accident! Fix the code so this is guaranteed. This fixes the following build error: ... relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol `nvtboot_boot_x0' ... Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: enable Ethernet on p2771-0000Stephen Warren2016-11-07-0/+5
| | | | | | | | | | | | | | | | | | Enable the Ethernet device in DT, provide board-specific configuration, and enable the driver in Kconfig. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DTStephen Warren2016-11-07-0/+20
| | | | | | | | | | | | | | | | | | Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the Tegra186 SoC DT so that boards can make use of it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: tegra: configure Ethernet address on Tegra186Stephen Warren2016-11-07-0/+55
| | | | | | | | | | | | | | | | | | | | | | On Tegra186, the bootloader which runs before U-Boot passes the Ethernet MAC address to U-Boot using device tree. Extract this value and write it to the environment, so that the Ethernet uclass picks it up and uses it for the built-in Ethernet device. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: tegra: add SoC-level hook for board_late_init()Stephen Warren2016-11-07-1/+6
|/ | | | | | | | | | | | | Extend the Tegra186 implementation of board_late_init() to call a per-SoC "hook" function. This will allow SoC-specific (rather than Tegra-wide) functionality to be implemented without the core Tegra code needing to be aware of the details. While board186.c is currently only used for Tegra186, it should be applicable to any other future SoC, and perhaps its simple design could be back-ported to older SoCs in the future too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* armv8: define get_ticks() for the ARMv8 Generic TimerAndre Przywara2016-11-05-0/+11
| | | | | | | | | | | | | | | | | | | For 64-bit ARM systems we provide just a timer_read_counter() implementation and rely on the generic non-uclass get_ticks() function in lib/time.c to call the former. However this function is actually not 64-bit safe, as it assumes a "long" to be 32-bit. Beside the fact that the resulting uint64_t isn't bigger than "long" on 64-bit architectures and thus combining two counters makes no sense, we get all kind of weird results when we try to OR in the high value shifted by _32_ bits. So let's avoid that function at all and provide a straight forward get_ticks() implementation for ARMv8, which also is in line with ARMv7. This fixes occasional immediate time-out expiration issues I see on the Pine64 board. The root cause of this needs to be investigated, but this fix looks like the right thing anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-11-02-64/+364
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| * rk3288: kconfig: remove duplicate definition of SPL_MMC_SUPPORTKever Yang2016-10-30-3/+0
| | | | | | | | | | | | | | | | | | SPL_MMC_SUPPORT defined in rockchip top level Kconfig instead of inside rk3288 and default to disable if ROCKCHIP_SPL_BACK_TO_BROM defined. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dts: rk3288: remove node in dmc which not need anymoreKever Yang2016-10-30-18/+0
| | | | | | | | | | | | | | | | | | | | Since we implement the dram capacity auto detect, we don't need to set the channel number and sdram-channel in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * rk3288: sdram: auto-detect the capacityKever Yang2016-10-30-42/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for rk3288 dram capacity auto detect, support DDR3 and LPDDR3, DDR2 is not supported. The program will automatically detect: - channel number - rank number - column address number - row address number The dts file do not need to describe those info after apply this patch. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
generated by cgit v1.1 at 2024-11-07 03:31:24 +0000