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* OMAP5: EMIF: Add support for DDR3 deviceLokesh Vutla2012-07-07-4/+166
| | | | | | | | | In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD precalculated timings for ddr3Lokesh Vutla2012-07-07-1/+55
| | | | | | | Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: Configure the io settings for omap5432 uevm boardLokesh Vutla2012-07-07-20/+93
| | | | | | This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD chip detection for OMAP5432 SOCLokesh Vutla2012-07-07-2/+12
| | | | | | This patch adds chip detection for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: Adding correct Control id code for OMAP5430Lokesh Vutla2012-07-07-1/+1
| | | | | | | Control id code for omap5430 ES1.0 is hard coded with a wrong value. This patch corrects the value Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* am33xx: Fix i2c sampling rate typoTom Rini2012-07-07-1/+1
| | | | | Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* am33xx: Fill in more cm_wkuppll / cm_perpllTom Rini2012-07-07-10/+30
| | | | | Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* am335x: Correct i2c sysc offsetTom Rini2012-07-07-3/+3
| | | | | Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* DaVinci: fix ddr2 vtp i/o calibrationTroy Kisky2012-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | Previously, only the low 5 bits (NCH) were being transfered from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed. VTP_RECAL should be bit 15, not 18. The only mainline board affected by this change is davinci_sonata. The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT. However, if the program that loads u-boot on these boards copied the code from u-boot, they will need fixed as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Please get tested by acks before applying, where tested by means an overnight memory test. Thanks Troy
* ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro.SRICHARAN R2012-07-07-1/+1
| | | | | | | OMAP5 evm board has 2GB of memory. So correct the macro to take in to account of the full dram size. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: Align memory used for testing to the power of 2SRICHARAN R2012-07-07-0/+3
| | | | | | | | | | | | get_ram_size checks the given memory range for valid ram, but expects the size of memory to be aligned to the power of 2. In case of OMAP5 evm board the memory available is 2GB - 16MB(used for TRAP section) = 2032MB. So always ensure that the size of memory used for testing is aligned to the power of 2. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: dmm: Create a tiler trap section.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | | | | | | | | | The unmapped entries in tiler space are set with values 0xFF. So creating a DMM section of size 16MB at 0xFF000000 with ADDRSPACE set to 0x2. This way all the unmapped entry accesses to tiler will be trapped by the EMIF and a error response is sent to the L3 interconnect. L3 errors are inturn reported to MPU. Note that here the tiler trap section is overlapping with the actual ddr physical space and we lose 16MB out of the total 2GB. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections.SRICHARAN R2012-07-07-2/+18
| | | | | | | | | | | | | The DMM sections can be overlapping with each other, with sections 3 to 0 having the highest to lowest priority in that order. There could also be a section that is used trap the unmapped Tiler entries and this trap section could be overlapping with the actual sdram area. So take care of the above scenarios while calculating the size of the actual ram. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* am33xx: Do not call init_timer twiceTom Rini2012-07-07-16/+16
| | | | | | | We do not need to call init_timer both in SPL and U-Boot itself, just SPL needs to initialize the timer. Signed-off-by: Tom Rini <trini@ti.com>
* arm: Tegra: Use ODMDATA from BCT in IRAMTom Warren2012-07-07-1/+25
| | | | | | | | | | | | | | | | Walk the BIT and BCT to find the ODMDATA word in the CustomerData field and put it into Scratch20 reg for use by kernel, etc. Built all Tegra builds OK; Booted on Seaboard and saw ODMDATA in PMC scratch20 was the same as the value in my burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities will have to specify the odmdata (nvflash --odmdata n) on the command line or via a cfg file, or built in to their BCT. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* gpio: tegra2: rename tegra2_gpio.* to tegra_gpio.*Tom Warren2012-07-07-3/+4
| | | | | | | | In anticipation of Tegra3 support, continue removing/renaming Tegra2-specific files. No functional changes (yet). Updated copyrights to 2012. Signed-off-by: Tom Warren <twarren@nvidia.com>
* spi: tegra2: rename tegra2_spi.* to tegra_spi.*Tom Warren2012-07-07-5/+4
| | | | | | | | In anticipation of Tegra3 support, start removing/renaming Tegra2-specific files. No functional changes (yet). Also updated copyright to 2012. Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: override compiler flags for low level init codeamartin@nvidia.com2012-07-07-2/+5
| | | | | | | | | | | | | | | Override -march setting for tegra to -march=armv4t for files that are necessary for low level init on tegra. The recent change to use -march=armv7-a for armv7 caused a regression on tegra because tegra starts boot on a arm7tdmi processor before transferring control to the cortex-a9. While still executing on the arm7tdmi there are calls to getenv_ulong() and memset() that cause an illegal instruction exception if compiled for armv7. Signed-off-by: Allen Martin <amartin@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Correct PLL access in ap20.c and clock.cSimon Glass2012-07-07-6/+9
| | | | | | | | | | | | | Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add SDMMC1 on SDIO1 funcmux entryStephen Warren2012-07-07-0/+8
| | | | | | | This will be used on TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add SDIO1 funcmux entry for UARTALucas Stach2012-07-07-0/+8
| | | | | | | | | | | | | | | This is based on top of: tegra: add alternate UART1 funcmux entry tegra: add UART1 on GPU funcmux entry v2: remove enum change Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren@nvidia.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: sync SDIO1 pingroup enum name with TRMLucas Stach2012-07-07-1/+1
| | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> CC: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add UART1 on GPU funcmux entryStephen Warren2012-07-07-1/+9
| | | | | | | TrimSlice uses UART1 on the GPU pingroup. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add alternate UART1 funcmux entryStephen Warren2012-07-07-2/+26
| | | | | | | | (In at least some configurations) Whistler uses UART1 on pingroups UAA, UAB. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* spi: Tegra2: Seaboard: fix UART corruption during SPI transactionsTom Warren2012-07-07-2/+2
| | | | | | | | | | | Simon Glass's proposal to fix this on Seaboard was NAK'd, so I removed his NS16550 references and added a small delay before SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes and saw no corruption (crc's matched) and no spurious comm chars. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
* omap3_dss: cosmetic changesJeroen Hofstee2012-05-25-20/+4
| | | | | | | | | | | Remove unnecessary brackets. Unwrap lines which are below 80 chars. Single line comment as single line (as the rest). Moved init values to the source code. cc: s-paulraj@ti.com cc: khasim@ti.com Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
* omap3_dss: add optional framebufferJeroen Hofstee2012-05-25-2/+35
| | | | | | | | | | | | | | The beagle board uses the background color to show an orange screen during startup. This patch adds the ability to add a frame buffer, with the intention not to break the beagle board use case (I don't have one). videomodes.c is not used. Scrolling depends on this patch: http://patchwork.ozlabs.org/patch/155662/ cc: trini@ti.com cc: s-paulraj@ti.com cc: khasim@ti.com Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
* mx53: Allow IPUv3 driver to also work on mx53Fabio Estevam2012-05-25-2/+6
| | | | | | | Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* LCD: support another s6e8ax0 panel typeDonghwa Lee2012-05-25-0/+1
| | | | | | | | | | | s6e8ax0 panel has many panel of types. This patch support another panel on TIZEN lunchbox board(HWREVISION 2). This panel has reversed panel display type. So, I had added necessary command. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* arch/arm/cpu/ixp/npe/npe.c: Fix build warningAnatolij Gustschin2012-05-22-1/+1
| | | | | | | | Fix: npe.c: In function 'npe_initialize': npe.c:630:13: warning: assignment from incompatible pointer type Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-05-20-0/+66
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: USB: S5P: Add ehci support usb:udc:samsung Add functions for storing private gadget data in UDC driver usb:gadget:composite: Support for composite at gadget.h usb:gadget:composite USB composite gadget support usb:udc:samsung:cleanup Replace DEBUG_* macros with debug_cond() calls usb:udc: Remove duplicated USB definitions from include/linux/usb/ch9.h file USB: Document the QH and qTD antics in EHCI-HCD USB: Drop cache flush bloat in EHCI-HCD USB: Drop ehci_alloc/ehci_free in ehci-hcd USB: Align buffers at cacheline usb: use noinline define
| * USB: S5P: Add ehci supportRajeshwari Shinde2012-05-20-0/+66
| | | | | | | | | | | | | | This patch adds ehci driver support for s5p. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2012-05-20-12/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-net: net: move bootfile init into eth_initialize net: punt bd->bi_ip_addr net: cosmetic: netconsole.c checkpatch compliance net: cosmetic: tftp.* checkpatch compliance net: cosmetic: sntp.* checkpatch compliance net: cosmetic: rarp.* checkpatch compliance net: cosmetic: nfs.* checkpatch compliance net: cosmetic: net.c checkpatch compliance net: cosmetic: eth.c checkpatch compliance net: cosmetic: bootp.* checkpatch compliance net: cosmetic: net.h checkpatch compliance net: Remove volatile from net API
| * | net: move bootfile init into eth_initializeMike Frysinger2012-05-15-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | All arches init this the same way, so move the logic into the core net code to avoid duplicating it everywhere else. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: punt bd->bi_ip_addrMike Frysinger2012-05-15-4/+0
| |/ | | | | | | | | | | | | | | | | This field gets read in one place (by "bdinfo"), and we can replace that with getenv("ipaddr"). After all, the bi_ip_addr field is kept up-to-date implicitly with the value of the ipaddr env var. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-05-20-784/+7511
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: (167 commits) OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT ARM: omap3: Set SPL stack size to 8KB, image to 54KB. arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree omap4: do not enable auxiliary cores omap4: do not enable fs-usb module omap4: panda: disable uart2 pads during boot igep00x0: change mpurate from 500 to auto igep00x0: enable the use of a plain text file tegra2: trivially enable 13 mhz crystal frequency tegra: Enable keyboard for Seaboard tegra: Switch on console mux and use environment for console tegra: Add tegra keyboard driver tegra: fdt: Add keyboard definitions for Seaboard tegra: fdt: Add keyboard controller definition tegra: Add keyboard support to funcmux input: Add support for keyboard matrix decoding from an fdt input: Add generic keyboard input handler input: Add linux/input.h for key code support fdt: Add fdtdec functions to read byte array tegra: Enable LP0 on Seaboard tegra: fdt: Add EMC data for Tegra2 Seaboard tegra: i2c: Add function to find DVC bus fdt: tegra: Add EMC node to device tree tegra: Add EMC settings for Seaboard tegra: Turn off power detect in board init tegra: Set up warmboot code on Nvidia boards tegra: Setup PMC scratch info from ap20 setup tegra: Add warmboot implementation tegra: Set up PMU for Nvidia boards tegra: Add PMU to manage power supplies tegra: Add EMC support for optimal memory timings tegra: Add header file for APB_MISC register tegra: Add tegra_get_chip_type() to detect SKU tegra: Add flow, gp_padctl, fuse, sdram headers tegra: Add crypto library for warmboot code tegra: Add functions to access low-level Osc/PLL details tegra: Move ap20.h header into arch location Add AES crypto library i2c: Add TPS6586X driver Add abs() macro to return absolute value fdt: Add function to return next compatible subnode fdt: Add function to locate an array in the device tree i.MX28: Avoid redefining serial_put[cs]() i.MX28: Check if WP detection is implemented at all i.MX28: Add battery boot components to SPL i.MX28: Reorder battery status functions in SPL i.MX28: Add LRADC init to i.MX28 SPL i.MX28: Add LRADC register definitions i.MX28: Shut down the LCD controller before reset i.MX28: Add LCDIF register definitions i.MX28: Implement boot pads sampling and reporting i.MX28: Improve passing of data from SPL to U-Boot M28EVK: Add SD update command M28EVK: Implement support for new board V2.0 FEC: Abstract out register setup MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged i.MX28: Add delay after CPU bypass is cleared spi: mxs: Allow other chip selects to work spi: mxs: Introduce spi_cs_is_valid() mx53loco: Remove unneeded gpio_set_value() mx53loco: Add CONFIG_REVISION_TAG mx53loco: Turn on VUSB regulator mx53loco: Add mc34708 support and set mx53 frequency at 1GHz pmic: dialog: Avoid name conflicts imx: Add u-boot.imx as target for ARM9 i.MX SOCs i.MX2: Include asm/types.h in arch-mx25/imx-regs.h imx: usb: There is no such register i.MX25: usb: Set PORTSCx register imx: nand: Support flash based BBT i.MX25: This architecture has a GPIO4 too i.MX25: esdhc: Add mxc_get_clock infrastructure i.MX6: mx6q_sabrelite: add SATA bindings i.MX6: add enable_sata_clock() i.MX6: Add ANATOP regulator init mx28evk: add NAND support USB: ehci-mx6: Fix broken IO access M28: Scan only first 512 MB of DRAM to avoid memory wraparound Revert "i.MX28: Enable additional DRAM address bits" M28: Enable FDT support mx53loco: Add support for 1GHz operation for DA9053-based boards mx53loco: Allow to print CPU information at a later stage mx5: Add clock config interface imx-common: Factor out get_ahb_clk() i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow mx31pdk: Allow booting a zImage kernel mx6qarm2: Allow booting a zImage kernel mx6qsabrelite: Allow booting a zImage kernel mx28evk: Allow booting a zImage kernel m28evk: Allow to booting a dt kernel mx28evk: Allow to booting a dt kernel mx6qsabrelite: No need to set the direction for GPIO3_23 again pmic: Add support for the Dialog DA9053 PMIC MX53: mx53loco: Add SATA support MX53: Add support to ESG ima3 board SATA: add driver for MX5 / MX6 SOCs MX53: add function to set SATA clock to internal SATA: check for return value from sata functions MX5: Add definitions for SATA controller NET: fec_mxc.c: Add a way to disable auto negotiation Define UART4 and UART5 base addresses EXYNOS: Change bits per pixel value proper for u-boot. EXYNOS: support TRATS board display function LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI EXYNOS: support EXYNOS MIPI DSI interface driver. EXYNOS: support EXYNOS framebuffer and FIMD display drivers. LCD: add data structure for EXYNOS display driver EXYNOS: add LCD and MIPI DSI clock interface. EXYNOS: definitions of system resgister and power management registers. SMDK5250: fix compiler warning misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998 misc:pmic:max8997 MAX8997 support for PMIC driver TRATS: modify the trats's configuration ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT cm-t35: add I2C multi-bus support include/configs: Remove CONFIG_SYS_64BIT_STRTOUL include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF omap3: Introduce weak misc_init_r omap730p2: Remove empty misc_init_r omap5912osk: Remove empty misc_init_r omap4+: Remove CONFIG_ARCH_CPU_INIT omap4: Remove CONFIG_SYS_MMC_SET_DEV OMAP3: pandora: drop console kernel argument OMAP3: pandora: revise GPIO configuration ...
| * | arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xxMatt Porter2012-05-15-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com>
| * | omap4: do not enable auxiliary coresTero Kristo2012-05-15-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Booting up these cores (dsp / ivahd / cortex-m3) is bad without firmware running on them, and they will hang preventing any kind of sleep transitions later on with the kernel. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: R Sricharan <r.sricharan@ti.com>
| * | omap4: do not enable fs-usb moduleTero Kristo2012-05-15-2/+0
| | | | | | | | | | | | | | | | | | | | | If this is done in the bootloader, the FS-USB will later be stuck into intransition state, which will prevent the device from entering idle. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * | tegra2: trivially enable 13 mhz crystal frequencyLucas Stach2012-05-15-1/+4
| | | | | | | | | | | | | | | | | | | | | This is needed for upcoming Toradex Colibri T20 upstream support. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: fdt: Add keyboard controller definitionAnton Staff2012-05-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The Tegra keyboard controller provides a simple interface to a matrix keyboard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add keyboard support to funcmuxSimon Glass2012-05-15-0/+16
| | | | | | | | | | | | | | | | | | | | | Add funcmux support for the default keyboard mapping. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: i2c: Add function to find DVC busSimon Glass2012-05-15-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus. This allows us to talk to the PMU. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | fdt: tegra: Add EMC node to device treeSimon Glass2012-05-15-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a definition of the memory controller node according to the bindings here: http://patchwork.ozlabs.org/patch/132928/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Setup PMC scratch info from ap20 setupYen Lin2012-05-15-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Save SDRAM parameters into the warmboot scratch registers Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add warmboot implementationYen Lin2012-05-15-0/+869
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to set up the warm boot area in the Tegra CPU ready for a resume after suspend. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add PMU to manage power suppliesJimmy Zhang2012-05-15-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power supplies must be adjusted in line with clock frequency. This code provides a simple routine to set the voltage to allow operation at maximum frequency. - Split PMU code into separate TPS6586X driver Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add EMC support for optimal memory timingsJimmy Zhang2012-05-15-0/+400
| | | | | | | | | | | | | | | | | | | | | | | | Add support for setting up the memory controller parameters. Boards can set up an appropriate table in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add header file for APB_MISC registerSimon Glass2012-05-15-0/+36
| | | | | | | | | | | | | | | | | | | | | Add a basic header file for this register, to be filled in as needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add tegra_get_chip_type() to detect SKUSimon Glass2012-05-15-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to know which type of chip we are running on - the Tegra family has several SKUs. This can be determined by reading a fuse register, so add this function to ap20. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-09-23 18:22:23 +0000