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* arm: socfpga: nic301: Add NIC-301 GPV register fileMarek Vasut2014-10-06-0/+195
| | | | | | | | | | | | | Add register definition for the NIC-301 used on SoCFPGA. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: scu: Add SCU register fileMarek Vasut2014-10-06-0/+23
| | | | | | | | | | | | | Add the Snoop Control Unit register definition file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: sysmgr: Add FPGA bits into system managerMarek Vasut2014-10-06-0/+39
| | | | | | | | | | | | | | Add missing system manager bits from Altera U-Boot to make the code comparable. These are the bits which depend on the FPGA manager. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: reset: Add function to reset FPGA bridgesMarek Vasut2014-10-06-0/+40
| | | | | | | | | | | | | | | | Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: fpga: Add SoCFPGA FPGA programming interfacePavel Machek2014-10-06-1/+193
| | | | | | | | | | | | | | | | | | | Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
* arm: socfpga: misc: Align print_cpuinfo() outputPavel Machek2014-10-06-1/+1
| | | | | | | | | | | | | | Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: misc: Add SD controller initPavel Machek2014-10-06-0/+13
| | | | | | | | | | | | | | Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: misc: Add proper ethernet initializationPavel Machek2014-10-06-15/+52
| | | | | | | | | | | | | | | | | | | | | Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: reset: Add EMAC reset functionsMarek Vasut2014-10-06-0/+20
| | | | | | | | | | | | | | | Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: timer: Pull the timer reload value from config fileMarek Vasut2014-10-06-0/+2
| | | | | | | | | | | | | | | | The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Sync with reference codeMarek Vasut2014-10-06-16/+29
| | | | | | | | | | | | | | | Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Clean up bit definitionsMarek Vasut2014-10-06-303/+323
| | | | | | | | | | | | | | Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Trim down code duplicationMarek Vasut2014-10-06-58/+38
| | | | | | | | | | | | | | | Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Add code to read clock configurationPavel Machek2014-10-06-3/+266
| | | | | | | | | | | | | | | | | | Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)
* arm: socfpga: clock: Drop nonsense inlining from clock manager codeMarek Vasut2014-10-06-6/+6
| | | | | | | | | | | | | | | | The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Implant order into bit definitionsMarek Vasut2014-10-06-67/+99
| | | | | | | | | | | | | | The bit definitions for clock manager are complete chaos. Implement some basic logical order into them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: sysmgr: Clean up system managerMarek Vasut2014-10-06-34/+86
| | | | | | | | | | | | | | Clean up the system manager register definition and add the missing register definitions in place. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add watchdog disable for socfpgaPavel Machek2014-10-06-0/+30
| | | | | | | | | | | | | | | | This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
* arm: socfpga: Clean up base address fileMarek Vasut2014-10-06-51/+51
| | | | | | | | | | | | | | | Sort the list of functional block addresses and fix indentation. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* arm: socfpga: Complete the list of base addressesPavel Machek2014-10-06-0/+40
| | | | | | | | | | | | | | | Add base addresses for all subsystems as documented in the Cyclone V HPS documentation. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* arm: cache: Add support for write-allocate D-CacheMarek Vasut2014-10-06-0/+3
| | | | | | | | | | | | | | Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-90/+525
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| * board/ls1021aqds: Add DDR4 supportYork Sun2014-09-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
| * armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun2014-09-25-89/+518
| | | | | | | | | | | | | | | | | | | | Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory blockYork Sun2014-09-25-1/+2
| | | | | | | | | | | | | | DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun <yorksun@freescale.com>
* | kconfig: move CONFIG_OF_* to KconfigMasahiro Yamada2014-09-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit moves: CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_OF_EMBED CONFIG_OF_HOSTFILE Because these options are currently not supported for SPL, the "Device Tree Control" menu does not appear in the SPL configuration. Note: zynq-common.h should be adjusted so as not to change the default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-21/+21
| | | | | | | | | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | arm: kirkwood: spi.h: Add some missing parenthesisStefan Roese2014-09-24-4/+4
|/ | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-21-0/+78
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| * ARM: keystone: ddr3: workaround for ddr3a/3b memory issueMurali Karicheri2014-09-17-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | ARM: atmel: add pcr related definitionBo Shen2014-09-19-1/+2
| | | | | | | | | | | | | | | | Using CPU_HAS_PCR micro to present the SoC has pcr (peripheral control register). Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ARM: atmel: use pcr to enable or disable peripheral clockBo Shen2014-09-19-4/+25
| | | | | | | | | | | | | | | | When use pcr (peripheral control register), then we won't need to care about the peripheral ID. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ARM: atmel: sama5d3: add timings registerBo Shen2014-09-19-1/+2
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-17-165/+313
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| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-17-165/+313
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| | * imx: Fix build of mx6sxsabresdStefano Babic2014-09-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 224beb833e544b802f08765271cec07667d39669 add clock enabling function for FEC, but the masks are not available for SX processor and the mx6sxsabresd cannot be built clean. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Nikita Kiryanov <nikita@compulab.co.il>
| | * pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-4/+22
| | | | | | | | | | | | | | | | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mx6: imx-regs: Provide a structure for GPC registersFabio Estevam2014-09-09-0/+13
| | | | | | | | | | | | | | | | | | | | | Introduce a structure for accessing the General Power Controller block (GPC) registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6qsabreauto: Remove imx6q-sabreauto.dtsFabio Estevam2014-09-09-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fa9c021632473 ("mx6: add example DTB for mx6qsabreauto") introduced 'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains the 'model' and 'compatible' strings. After this commit the final binary is also changed from 'u-boot.imx' to 'u-boot-dtb.imx', which may confuse users. So revert it until a more complete and useful device tree could be provided. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov2014-09-09-4/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| | * iMX6: Disable the L2 before chaning the PL310 latencyYe.Li2014-09-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
| | * arm: mx6: add support for Compulab cm-fx6 CoMNikita Kiryanov2014-09-09-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: add get_cpu_type()Nikita Kiryanov2014-09-09-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Define get_cpu_type(). Reuse it in is_cpu_type(). Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: fix cs0_end calculationNikita Kiryanov2014-09-09-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value. This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed. Refactor the calculation. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: configure MMDC for slow_pdNikita Kiryanov2014-09-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for 'slow exit (DLL off)' (MR0[12] = 0). Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
| | * arm: mx6: ddr: do not write into reserved bitNikita Kiryanov2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: cleanupNikita Kiryanov2014-09-09-141/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * i2c: imx: add macros to setup pads for multiple SoC typesNikita Kiryanov2014-09-09-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * mx6: add clock enabling functionsNikita Kiryanov2014-09-09-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | | Revert "ARM: SPL: do not set gd again"Tom Rini2014-09-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the high level, the problem is that we set gd multiple times (and still do, even after the commit we're reverting). We set important parts of gd to the copy which is not above stack but rather in the data section. For the release, we're going to revert this change and for the next release we shall correct things to only, really, set gd once to an appropriate location and ensure that comments about it are correct too. This reverts commit f0c3a6c4ad09210d5d4aeafe87685ee75e5683d6. Acked-by: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@ti.com>
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