summaryrefslogtreecommitdiff
path: root/arch/arm
Commit message (Collapse)AuthorAgeLines
* sunxi: add sun7i clocks and timer support.Ian Campbell2014-05-25-0/+727
| | | | | | | | | | | | | | | | | | | | | | This patch adds the basic clocks and timer support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Some of the code here is common to multiple sunxi subarchtectures, hence files are named sun4i which is the earliest similar variant. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: vf610: add DDR_SEL_PAD_CONTR registerStefan Agner2014-05-25-0/+1
| | | | | | | | Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual. Signed-off-by: Stefan Agner <stefan@agner.ch>
* Arm64 fix a bug of vbar_el3 initializationDavid Feng2014-05-25-2/+2
| | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-24-263/+470
|\
| * am33xx: report silicon revision instead of codeSergey Alyoshin2014-05-23-18/+23
| | | | | | | | | | | | | | | | | | As revision code 1 is for silicon revision 2.0, it is easily confused with silicon revision 1.0. Device type report also reworked in same style. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
| * ARM: OMAP: Fix omap_sdram_size calculationLokesh Vutla2014-05-23-4/+7
| | | | | | | | | | | | | | | | | | Last section of DMM is used for trapping tiler unmapped sections. Corresponding trap_size should be deducted from total SDRAM size only if trap section is overlapping with available SDRAM based on DMM sections. Fixing the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * armv7:TI: Add <asm/ti-common/sys_proto.h> and migrate omap_hw_init_contextTom Rini2014-05-23-112/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | The omap_hw_init_context function (and assorted helpers) is the same for all OMAP-derived parts as when CHSETTINGS are used, that's the same and our DDR base is also always the same. In order to make this common we simply need to update the names of the define for DDR address space which is also common. Cc: Sricharan R. <r.sricharan@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: ctrl: Fix efuse register addressesLokesh Vutla2014-05-23-4/+4
| | | | | | | | | | | | | | | | Efuse register addresses are wrongly programmed. Fixing the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: Update EMIF dataLokesh Vutla2014-05-23-3/+23
| | | | | | | | | | | | | | | | DRA72 has 1GB connected to EMIF1 only. Updating the details. And also enable WA for BUG0039 only if corresponding EMIF is present. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: clocks: Update the hwdataLokesh Vutla2014-05-23-0/+7
| | | | | | | | | | | | | | Adding the prcm, dplls, control module hooks for DRA72x. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: volt: Update the pmic offsetsKeerthy2014-05-23-0/+32
| | | | | | | | | | | | | | | | TPS65917 is used in DRA722 evm. Update the address offsets accordingly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: Add Silicon ID supportLokesh Vutla2014-05-23-0/+5
| | | | | | | | | | | | | | Add silicon ID code for DRA722 silicon. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: omap: merge GPMC initialization code for all platformpekon gupta2014-05-23-110/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC controller on TI's OMAP SoC is general purpose controller to interface with different types of external devices like; - parallel NOR flash - parallel NAND flash - OneNand flash - SDR RAM - Ethernet Devices like LAN9220 Though GPMC configurations may be different for each platform depending on clock-frequency and external device interfacing with controller. But initialization sequence remains common across all platfoms. Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c files into single omap-common/mem-common.c However, actual platforms specific register config values are still sourced from corresponding platform specific headers like; AM33xx: arch/arm/include/asm/arch-am33xx/mem.h OMAP3: arch/arm/include/asm/arch-omap3/mem.h OMAP4: arch/arm/include/asm/arch-omap4/mem.h OMAP4: arch/arm/include/asm/arch-omap5/mem.h Also, CONFIG_xx passed by board-profile decide config for which set of macros need to be used for initialization CONFIG_NAND: initialize GPMC for NAND device CONFIG_NOR: initialize GPMC for NOR device CONFIG_ONENAND: initialize GPMC for ONENAND device Signed-off-by: Pekon Gupta <pekon@ti.com> [trini: define GPMC_SIZE_256M for omap3] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: omap5: add platform specific info for GPMC and ELM controllerspekon gupta2014-05-23-6/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves platform specific information for GPMC and ELM controller into separate header files, so that any derivative devices do not mess other header files. Platform specific information added into arch-xx/../hardware.h - CPU related platform specific details like base-address of GPMC and ELM Platform specific information added into arch-xx/../mem.h - Generic configs for GPMC and ELM initialization. - Hardware parameters or constrains specific to GPMC and ELM IP like; number of max number of chip-selects available Signed-off-by: Pekon Gupta <pekon@ti.com>
| * ARM: omap4: add platform specific info for GPMC and ELM controllerspekon gupta2014-05-23-6/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves platform specific information for GPMC and ELM controller into separate header files, so that any derivative devices do not mess other header files. Platform specific information added into arch-xx/../hardware.h - CPU related platform specific details like base-address of GPMC and ELM Platform specific information added into arch-xx/../mem.h - Generic configs for GPMC and ELM initialization. - Hardware parameters or constrains specific to GPMC and ELM IP like; number of max number of chip-selects available Signed-off-by: Pekon Gupta <pekon@ti.com>
* | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-7/+16
|\ \
| * | arm: rmobile: koelsch: Fix QoS revision 0.240 and 0.320Nobuhiro Iwamatsu2014-05-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add register define of DBSC3 operation adjustment register, and add initial value. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: rmobile: r8a7791: Fix MOD_SEL3 function table about FN_SEL_IEBNobuhiro Iwamatsu2014-05-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | FN_SEL_IEB is assigned 2bit, and 2bit can represent 4 patterns. However FN_SEL_IEB but we only use 3. It adds empty patterns as 0. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | gpio: r8a7790-gpio: Fix typo in macroNobuhiro Iwamatsu2014-05-21-3/+3
| | | | | | | | | | | | | | | | | | Fix typo from __ASM_R8A7790_H__ to __ASM_R8A7790_GPIO_H__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | gpio: r8a7791-gpio: Fix typo in macroNobuhiro Iwamatsu2014-05-21-3/+3
| | | | | | | | | | | | | | | | | | Fix typo from __ASM_R8A7791_H__ to __ASM_R8A7791_GPIO_H__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: rmobile: Add define of SCIF register for R8A7790 and R8A7791Nobuhiro Iwamatsu2014-05-21-0/+8
| |/ | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-9/+383
|\ \
| * | zynq: add UART nodes to device tree to initialize UART with OFMasahiro Yamada2014-05-15-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c9416b92 added OF UART initialization support but aliases nodes are missing in device tree. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board] Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: add memory nodes to device tree to initialize DRAM with OFMasahiro Yamada2014-05-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9e0e37ac added OF RAM initialization support but memory nodes are missing in device tree. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board] Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: import zynq-7000.dtsi from Linux KernelMasahiro Yamada2014-05-15-0/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our current motivation is to use OF initialization for RAM and UART. But adding full DTS would be helpful in future, for instance, for OF configuration of Ethernet, MMC, USB, etc. This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5 and adjusts the license comment block for SPDX. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: treat ps7_init.c/h as external files to ignore themMasahiro Yamada2014-05-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ps7_init.c and ps7_init.h are supposed to be exported by hw project and copied to board/xilinx/zynq/ directory. We want them to be ignored by git. So what we should do is to always treat them as external files rather than replacing ps7_init.c This commit does: - Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c and delete board/xilinx/zynq/ps7_init.c - Compile board/xilinx/zynq/ps7_init.c only when it exists - Add .gitignore to ignore ps7_init.c/h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: ehci: Added USB host driver supportMichal Simek2014-05-14-0/+26
| | | | | | | | | | | | | | | | | | | | | Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Add MIO detection codeMichal Simek2014-05-14-0/+51
| | | | | | | | | | | | | | | | | | | | | Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Fix bootmode maskMike Looijmans2014-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bootmode mask was defined as 0x0F, but documentation mentions 0x07. Experiments show that bit "3" is the JTAG chain configuration. Change the mask to "7" to allow systems with a different chain configuration to boot correctly. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Setup correct slcr_lock valueMichal Simek2014-05-14-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | The driver should setup slcr state according to slcr operations. Reported-by: Andrey Filippov <andrey@elphel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: slcr: Fix incorrect commentaryMichal Simek2014-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix c&p error in zynq_slcr_devcfg_enable() commentary and extending it with description according to Zynq TRM also in zynq_slcr_devcfg_disable(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Call zynq board_init() in SPLMichal Simek2014-05-14-0/+7
| | | | | | | | | | | | | | | | | | Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | ARM: zynq: Do not use half memory size for ECC caseMichal Simek2014-05-14-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Memory size should be specified without ECC place. If you need to have half memory size, please change u-boot configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Added efuse status register base addressSiva Durga Prasad Paladugu2014-05-14-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Fix sparse warning in ddrc.cMichal Simek2014-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | Warning: arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Fix sparse warnings in slcr.cMichal Simek2014-05-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warnings: arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-05-22-4478/+4045
|\ \ \ | | |/ | |/|
| * | Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2014-05-20-2/+2
| |\ \ | | |/ | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
| * | Merge remote-tracking branch 'u-boot-sh/rmobile'Albert ARIBAUD2014-05-16-1286/+706
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Trivial conflict, maintainer change plus board addition
| | * | arm: rmobile: Add register infomation of PLL regsiterNobuhiro Iwamatsu2014-04-28-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: r8a7791: Add support ES2 revisionNobuhiro Iwamatsu2014-04-28-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is ES2 is a new revision to R8A7791. This adds support this revision. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: r8a7790: Add support ES2 revisionNobuhiro Iwamatsu2014-04-28-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is ES2 is a new revision to R8A7790. This adds support this revision. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: Update print_cpuinfo functionNobuhiro Iwamatsu2014-04-28-27/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The print_cpuinfo fucntion has same code. It has a code of many common. This adds a table of CPU information, duplicate using for-loop. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: Add prototype for function to get the CPU information to rmobile.hNobuhiro Iwamatsu2014-04-28-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions are defined but has no prototype declaration. Add them. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: Add rmobile_get_cpu_rev_fraction() for R-Car SoCsNobuhiro Iwamatsu2014-04-28-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds rmobile_get_cpu_rev_fraction to get fraction revision for R-Car SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: Add 1 to value of the CPU revision in ↵Nobuhiro Iwamatsu2014-04-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rmobile_get_cpu_rev_integer() Value that can be obtained in the rmobile_get_cpu_rev_integer() starts at 0. However, revisions to start from 1, which adds 1. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: Merge functions to get the CPU information of R8A7790 and R8A7791Nobuhiro Iwamatsu2014-04-28-34/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Functions to get the CPU information of R8A7790 and R8A7791 are common. This merges these as cpu_info-rcar.c. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: r8a779x: Fix L2 cache init and latency settingNobuhiro Iwamatsu2014-04-28-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L2CTLR only need to update for cluster 0. This changes L2CTLR to initialize only when cluster is 0. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | arm: rmobile: Coordinate the common part of the header file of r8a7790 and ↵Nobuhiro Iwamatsu2014-04-28-1224/+640
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r8a7791 Header files of R8A7790 and R8A7791 have common part of many. This coordinates as rcar-base.h. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-16-5/+287
| |\ \ \
generated by cgit v1.1 at 2024-11-05 18:43:53 +0000