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* mxs: regs-common.h must be wrapped with !__ASSEMBLY__Peng Fan2015-11-12-1/+1
| | | | | | | regs-common.h must be wrapped with #ifndef __ASSEMBLY__ Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: add parameter base_addr for mxs_set_lcdclkPeng Fan2015-11-12-2/+2
| | | | | | | | | | | Change mxs_set_lcdclk prototype to add a new parameter base_addr. There are two LCD interfaces for i.MX6SX, we may support LCDIF1 or LCDIF2. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* mx7: psci: add basic psci supportPeng Fan2015-11-12-0/+139
| | | | | | | | | | | | 1. add basic psci support for imx7 chip. 2. support cpu_on and cpu_off. 3. switch to non-secure mode when boot linux kernel. 4. set csu allow accessing all peripherial register in non-secure mode. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* arm: discard relocation entries for secure textPeng Fan2015-11-12-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code such as PSCI in section named secure is bundled with u-boot image, and when bootm, the code will be copied to their runtime address same to compliation/linking address - CONFIG_ARMV7_SECURE_BASE. When compile the PSCI code and link it into the u-boot image, there will be relocation entries in .rel.dyn section for PSCI. Actually, we do not needs these relocation entries. If still keep the relocation entries in .rel.dyn section, r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid address which may not support read/write for one SoC. 102 /* relative fix: increase location by offset */ 103 add r0, r0, r4 104 ldr r1, [r0] 105 add r1, r1, r4 106 str r1, [r0] So discard them to avoid touching the relocation entry in arch/arm/lib/relocate.S. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Tom Warren <twarren@nvidia.com> Cc: York Sun <yorksun@freescale.com> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge git://git.denx.de/u-bootStefano Babic2015-11-12-773/+4042
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| * ARM: uniphier: drop UniPhier specific SMP codeMasahiro Yamada2015-11-11-61/+0
| | | | | | | | | | | | | | | | | | | | | | The latest Linux can directly handle SMP operations for UniPhier SoCs without any help of U-boot. Drop the relevant code from U-boot. See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier: rework SMP operations to use trampoline code") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * ARM: dts: uniphier: add USB xHCI nodes for PH1-Pro5 and ProXstream2Masahiro Yamada2015-11-11-0/+60
| | | | | | | | | | | | | | This makes USB3.0 available on new SoCs/boards. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: dts: uniphier: fix interrupt number of USB core for PH1-Pro4Masahiro Yamada2015-11-11-1/+1
| | | | | | | | | | | | | | The IRQ is not used in U-Boot, but this would be useful to sync device trees between Linux and U-Boot. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-11-10-12/+300
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| | * ARM: tegra: add custom MMU setup on ARMv8Stephen Warren2015-11-10-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sets up a fine-grained page table, which is a requirement for noncached_init() to operate correctly. MMU setup code currently exists in a number of places: - A version in the core ARMv8 support code that sets up page tables that use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't support. - Enhanced versions for fsl-lsch3 and zynmq that set up finer grained page tables. Ideally, rather than duplicating the MMU setup code yet again this patch would instead consolidate all the different routines into the core ARMv8 code so that it supported all use-cases. However, this will require significant effort since there appear to be a number of discrepancies[1] between different versions of the code, and between the defines/values by some copies of the MMU setup code use and the architectural MMU documentation. Some reverse engineering will be required to determine the intent of the current code. [1] For example, in the core ARMv8 MMU setup code, three defines named TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and the others set a different field (T1SZ) in the page tables. As far as I can tell so far, there should be no need to set different values per exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't be enabled anyway. Another example is inconsistent values for *_VA_BITS between the current core ARMv8 MMU setup code and the various SoC- specific MMU setup code. Another example is that asm/armv8/mmu.h's value for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT; research is needed to determine which code relies on which of those values and why, and whether fixing the incorrect value will cause any regression. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * armv8: allow custom MMU setup routines on ARMv8Stephen Warren2015-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order for noncached_init() to operate correctly, SoCs must set up a custom page table with fine-grained (2MiB) sections, which can be configured from noncached_init(). This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There are some other reasons for the duplication there though, such as enabling icache early, and enabling dcaching earlier with a different configuration. This change makes mmu_setup() a weak implementation, so that the MMU setup code can be replaced without having to duplicate other code that calls it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORYStephen Warren2015-11-10-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * arm: stm32f4: fix a bug when a random sector gets erasedVadzim Dambrouski2015-11-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Old sector number is not being cleared from FLASH_CR register. For example when first erased sector was 001 and then you want to erase sector 010, sector 011 gets erased instead. This patch clears old sector number from FLASH_CR register before a new one is written. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| | * arm: stm32f4: fix a bug when only first sector gets erasedVadzim Dambrouski2015-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | flash_lock call is inside a for loop, so after the first iteration flash is locked and no more sectors can be erased. Move flash_lock out of the loop. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| | * Revive OpenRD targetsAlbert ARIBAUD2015-11-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert commit 7a2c1b13 which dropped OpenRD boards. Assume maintainership of OpenRD. Remove OpenRD from scrapyard. Switch OpenRD to generic board. Switch to Thumb build. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| | * kirkwood: support CONFIG_SYS_THUMB_BUILDAlbert ARIBAUD2015-11-10-0/+6
| | | | | | | | | | | | | | | | | | | | | Kirkwood files cpu.c and cache.c cannot build in Thumb state; force them in ARM state even under CONFIG_SYS_THUMB_BUILD. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| | * arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILDAlbert ARIBAUD2015-11-10-3/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| | * arm: fix compile warnings when semihosting is enabled on ARMv7M target.Vadzim Dambrouski2015-11-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes compile warnings like this: warning: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' In C99 standard you can use %zu modifier to print size_t values. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| | * arm: add support for semihosting for ARMv7M targetsVadzim Dambrouski2015-11-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile error looking like this: arch/arm/lib/semihosting.c: In function 'smh_read': {standard input}: Assembler messages: {standard input}:34: Error: invalid swi expression {standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0 scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed The source of the problem is "svc #0x123456" instruction. This instruction can not be encoded using Thumb2 instruction set used by ARMv7M CPUs. ARM documentation suggests using "bkpt #0xAB" instruction instead [1]. This patch fixes compile errors and adds support for semihosting for STM32F429 or any other ARMv7M target. This change was sested on STM32F429-DISCOVERY board using OpenOCD and "smhload" u-boot command. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| * | Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-22/+62
| |/ | | | | | | | | | | | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARM64: zynqmp: Sync zynq_sdhci_init() declarationMichal Simek2015-11-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix compilation error: drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for ‘zynq_sdhci_init’ int zynq_sdhci_init(phys_addr_t regbase) ^ In file included from drivers/mmc/zynq_sdhci.c:14:0: ./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration of ‘zynq_sdhci_init’ was here int zynq_sdhci_init(unsigned long regbase); ^ Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * compat: Remove is_power_of_2() definitionFabio Estevam2015-11-05-1/+1
| | | | | | | | | | | | | | | | | | | | Use the is_power_of_2() definition from log2.h to align with the kernel implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: Use the generic bitops headersFabio Estevam2015-11-05-0/+5
| | | | | | | | | | | | | | | | | | | | The generic bitops headers are required when calling logarithmic functions, such as ilog2(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * Merge git://git.denx.de/u-boot-samsungTom Rini2015-11-05-24/+100
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| | * arm: exynos: clean up checkpatch issuesMinkyu Kang2015-11-02-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will fix these checkpatch issues. ERROR: Macros with complex values should be enclosed in parentheses +#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) ERROR: space prohibited before that ',' (ctx:WxW) + writel(val , &drex0->concontrol); ^ ERROR: space prohibited before that ',' (ctx:WxW) + writel(val , &drex1->concontrol); ^ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos4412: pinmux: disable pull for MMC pinsPrzemyslaw Marczak2015-11-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 8 pins for SD card in Exynos, but the MUX was configured only for 7, since the one was used for card detection. This caused the pin's pull wrong configuration. This commit fixes this and the card detect can work properly, after call this function. Tested-on: Odroid U3 and Odroid X2. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Odroid-XU3: dts: enable ADC, with request for pre-reloc bindPrzemyslaw Marczak2015-11-02-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This ADC is required for Odroid's board revision detection. The pre-reloc request is enabled, since board detection will be done in one of early function call. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos54xx: dts: add ADC nodePrzemyslaw Marczak2015-11-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds common ADC node, which is disabled as default. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Odroid-XU3: enable s2mps11 PMIC supportPrzemyslaw Marczak2015-11-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * dm: adc: add Exynos54xx compatible ADC driverPrzemyslaw Marczak2015-11-02-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds driver for Exynos54xx ADC subsystem. The driver is implemented using driver model, amd provides ADC uclass's methods for ADC single channel operations: - adc_start_channel() - adc_channel_data() - adc_stop() The basic parameters of ADC conversion, are: - sample rate: 600KSPS - output the data as average of 8 time conversion ADC features: - sample rate: 600KSPS - resolution: 12-bit - channels: 10 (analog multiplexer) Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5422/5800: set cpu id to 0x5422Przemyslaw Marczak2015-11-02-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The proper CPU ID for those Exynos variants is 0x5422, but before the 0x5800 was set. This commit fix this back. Changes: - set cpu id to 0x5422 instead of 0x5800 - remove macro proid_is_exynos5800() - add macro proid_is_exynos5422() - change the calls to proid_is_exynos5800() with new macro Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Peach-Pi: dts: add cpu-model stringPrzemyslaw Marczak2015-11-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This platform is based on Exynos5800 but the cpu id is 0x5422. This doesn't fit the common Exynos SoC name convention, so now, the CPU name is defined by device tree string, to be printed properly. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * s5p: cpu_info: print "cpu-model" if exists in dtsPrzemyslaw Marczak2015-11-02-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422). For such case, the CPU name should be defined in device tree. This commit introduces new device-tree property for Exynos: - "cpu-model" - with cpu name string If defined, then the cpu id is not printed. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-11-05-4/+4
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| | * | arm: dts: socfpga: Increase the spi-max-frequency for QSPI flashChin Liang See2015-11-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a working QSPI calibration, the SCLK can now run up to 100MHz Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * | arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit definesDinh Nguyen2015-11-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | | ARM: zynq: Remove zc70x targetMichal Simek2015-11-04-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove zc70x target which was one setting for zc702 and zc706. Currently zc702 and zc706 are separated. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | arm: zynq: Move serial driver to driver modelSimon Glass2015-11-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use driver model and change all users. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynqmp: Enable DM and OF bindingMichal Simek2015-11-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI requires DM and OF that's why enable DM for ZynqMP and start to use configuration based on embedded OF. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | arm: zynq: dts: Add U-Boot device tree additionsSimon Glass2015-11-04-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to mark some device tree nodes so that they are available before relocation. This enables driver model to find these automatically. In the case of SPL it ensures that these nodes will be retained in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | dm: arm: zynq: Enable device tree control in SPLSimon Glass2015-11-04-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to using device tree control in SPL so that we can use the same driver code in both SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm: zynq: Support the debug UARTSimon Glass2015-11-04-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the debug UART to assist with early debugging. Enable it for Zybo as an example. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm: zynq: Drop unnecessary code in SPL board_init_f()Simon Glass2015-11-04-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to the new way of starting up SPL. Clearing of BSS and calling board_init_r() is now handled by crt0.S. Also tidy up the header include order. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynqmp: Add DTS for ep108 boardMichal Simek2015-11-04-0/+963
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DTS for ep108 board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot
| * | | mmc: atmel: Add atmel sdhci supportWenyou Yang2015-11-03-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | arm: at91: clock: Add the generated clock supportWenyou Yang2015-11-03-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some peripherals may need a second clock source that may be different from the system clock. This second clock is the generated clock (GCK) and is managed by the PMC via PMC_PCR. For simplicity, the clock source of the GCK is fixed to PLLA_CLK. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | arm: at91: Change the Chip ID registers' addressesWenyou Yang2015-11-03-7/+10
| |/ / | | | | | | | | | | | | | | | | | | | | | Provide the specific addresses for the Chip ID and Chip ID Extension registers, instead of the offset, which make it use on other chips. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | at91: simplify spl board_init_f functionJosh Wu2015-11-01-5/+0
| |/ | | | | | | | | | | | | | | | | crt0.S do both memset the bss section and call board_init_r for us, so remove them from board_init_f(). Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-30-620/+2361
| |\
| | * arm: ls1021a: Add sata support on qds and twr boardtang yuantian2015-10-29-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-11 17:28:13 +0000