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* spl: common: Support for USB MSD FAT image loadingDan Murphy2014-01-24-3/+11
| | | | | | | | Add SPL support to be able to detect a USB Mass Storage device connected to a USB host. Once a USB Mass storage device is detected the SPL will load the u-boot.img from a FAT partition to target address. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: merge commonly-defined PLATFORM_RELFLAGSMasahiro Yamada2014-01-24-82/+2
| | | | | | | | | | | | | | Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8 had the same option: $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) This commit moves it into arch/arm/config.mk. If the compiler does not support the option, it is ignored by $(call cc-option,...). So this commit gives no harm to ARMv8. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* lib: time: add weak timer_init() functionDarwin Rambo2014-01-24-10/+0
| | | | | | | | | | If timer_init() is made a weak stub function, then it allows us to remove several empty timer_init functions for those boards that already have a timer initialized when u-boot starts. Architectures that use the timer framework may also remove the need for timer.c. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
* ARM: bcm2835: fix mailbox timeoutStephen Warren2014-01-20-1/+1
| | | | | | | | | | | My original intention was to have a 100ms timeout. However, the timer operations used return values in ms not us, so we ended up with a 100s timeout instead. Fixing this exposes that some operations need longer to operate than 100ms, so bump the timeout up to a whole second. Reported-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: rpi_b: power on SDHCI and USB HW modulesStephen Warren2014-01-20-0/+48
| | | | | | | | | | Send RPC commands to the VideoCore to turn on the SDHCI and USB modules. For SDHCI this isn't needed in practice, since the firmware already turned on the power in order to load U-Boot. However, it's best to be explicit. For USB, this is necessary, since the module isn't powered otherwise. This will allow the kernel USB driver to work. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-01-20-65/+0
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| * mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam2014-01-17-65/+0
| | | | | | | | | | | | | | | | | | Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-16-2/+21
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| * | arm: rmobile: Add SH QSPI base register addressNobuhiro Iwamatsu2014-01-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This adds base register address of SH QSPI. Currently, SH QSPI is used only from R8A7790 and R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-15-2/+19
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| | * mx6: Add initial support for the Hummingboard soloFabio Estevam2014-01-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SolidRun has designed the Hummingboard board based on mx6q/dl/solo. Add the initial support for the mx6 solo variant. More information about this hardware can be found at: http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware (Carrier-One was the previous name of Hummingboard). Based on the work from Jon Nettleton <jon.nettleton@gmail.com>. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()Fabio Estevam2014-01-15-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-14-6/+13
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| * | arm: use canonical sub mnemonicAndreas Bießmann2014-01-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building some arm boards with older binutils may produce errors like this: ---8<--- crt0.S: Assembler messages: crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)' --->8--- Use canonical version of the subtract mnemonic to avoid those issues. Reported-by: Alexey Smishlayev <alexey@xtech2.lv> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | Merge 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-14-1/+2
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| | * imx6: make use of lldiv(..)Christian Gmeiner2014-01-13-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 762a88ccf8540948fbf8c31b40a29d1e0684a25b introduces a 64-bit division without using the lldiv() function, which pulls in previously unused libgcc stuff. Signed-off-by: Måns Rullgård <mans@mansr.com> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | arm: put .hash, .got.plt and .machine_param back in binariesAlbert ARIBAUD2014-01-14-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some targets will build fine but not boot if sections .hash and .got.plt are not present in the binary. Add them back. Also, Exynos machines require .machine_param section in SPL. Add it. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-13-0/+13
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| * | ARM: pxa: Fix OneNAND SPL buildsMarek Vasut2014-01-13-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OneNAND SPL used on PXA is slightly obscure. Due to the OneNAND limitation, where we have only the first 1KiB of the OneNAND available upon power-up as a memory-mapped area, from which the CPU starts executing, we place only the most essential code into this first 1KiB . This code copies the rest of the SPL into SRAM and jumps to it. This code is stored in section .text.0 . The rest of the SPL is stored in section .text.1 . When running the OBJCOPY on the SPL, it will preserve only .text section, but the .text.0 and .text.1 are stripped away from the result, thus making the SPL binary empty. The patch adds additional -j parameters to the OBJCOPY for PXA during the SPL build, which will preserve the .text.0 and .text.1 sections. Moreover, this patch also adds missing functions into the .text.0 section, since otherwise the PXA270 with 1KiB-window OneNAND won't be able to boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com>
* | | usb: ehci: exynos: set/reset hsic physInderpal Singh2014-01-13-0/+14
|/ / | | | | | | | | | | | | | | The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-10-3900/+8531
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * | gpio: zynq: Add dummy gpio routinesJagannadha Sutradharudu Teki2014-01-10-0/+25
| | | | | | | | | | | | | | | | | | | | | GPIO dummy routines are required for fdt build, may be removed these dependencies once the u-boot fdt is fully optimized. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | dts: zynq: Add basic fdt supportJagannadha Sutradharudu Teki2014-01-10-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a basic fdt support for zynq u-boot. zynq-7000.dtsi-> initial arch dts file zynq-zed.dts -> initial zed board dts file more devices should be added in subsequent patches. u-boot build: once configuring of a board done for building dtb with zynq-zed.dts as an input zynq-uboot> make DEVICE_TREE=zynq-zed Enabled CONFIG_OF_SEPARATE for building dtb separately. There is a new binary called u-boot-dtb.bin which is a u-boot with devicetree supported. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | zynq: Add support to find bootmodeJagannadha Sutradharudu Teki2014-01-10-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | armv8: Use __aarch64__ rather than CONFIG_ARM64 in some casesTom Rini2014-01-10-18/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The toolchain sets __aarch64__ for both LE and BE. In the case of posix_types.h we cannot reliably use config.h as that will lead to problems. In the case of byteorder.h it's clearer to check the EB flag being set in either case instead. Cc: David Feng <fenghua@phytium.com.cn> Signed-off-by: Tom Rini <trini@ti.com> Amended by Albert ARIBAUD <albert.u.boot@aribaud.net> to actually remove the config.h include from the posix_types.h files, with permission from Tom Rini.
| * | arm64: core supportDavid Feng2014-01-09-21/+1819
| |/ | | | | | | | | | | | | Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-465/+3892
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| | * DTS: Add dts support for SMDK5420Rajeshwari Birje2013-12-30-190/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds dts support for SMDK5420. exynos5.dtsi created is a common file which has the nodes common to both 5420 and 5250. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-30-16/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-30-58/+484
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-30-202/+1679
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5420: Add dmc and phy_control register structureRajeshwari Birje2013-12-30-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5420: Add power register structure.Rajeshwari Birje2013-12-30-0/+837
| | | | | | | | | | | | | | | | | | | | | | | | Add structure for power register for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add base addresses for 5420Rajeshwari Birje2013-12-30-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds base addresses of various IPs and controllers required for Exynos5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5: Create a common board fileRajeshwari Birje2013-12-30-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-3308/+2329
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| | * arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-0/+16
| | | | | | | | | | | | | | | | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6Otavio Salvador2014-01-03-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The enable_fec_anatop_clock method should be available for all MX6 variant as it is not MX6 SoloLite specific. This moves the code out of the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| | * imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macroOtavio Salvador2014-01-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio Estevam <fabio.estevam@freescale.com> and Eric Bénard <eric@eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| | * mx6: soc: Disable VDDPU regulatorFabio Estevam2014-01-02-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: soc: Add the required LDO ramp up delayFabio Estevam2014-01-02-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: soc: Introduce set_ldo_voltage()Fabio Estevam2014-01-02-7/+26
| | | | | | | | | | | | | | | | | | Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: soc: Set the VDDSOC at 1.175 VFabio Estevam2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltagesFabio Estevam2014-01-02-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: soc: Staticize set_vddsoc()Fabio Estevam2014-01-02-3/+1
| | | | | | | | | | | | | | | | | | set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * MX6: fix sata compilation for i.MX6Stefano Babic2013-12-19-1/+2
| | | | | | | | | | | | | | | | | | | | | Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks board with SATA support, because sata is not compiled. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * imx6: fix random hang when download by usbFrank Li2013-12-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
| | * mx6: clock: Fix the calculation of PLL_ENET frequencyFabio Estevam2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * nitrogen6x: Move setup_sata to common partGiuseppe Pagano2013-12-17-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-2106/+2118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
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