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* stv0991: configure clock & pad muxing for qspiVikas Manocha2015-07-03-1/+34
| | | | | | | | stv0991 has cadence qspi controller for flash interfacing, this patch configures the device pads & clock for the controller. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-01-0/+35
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| * zynq: defconfig: Move CONFIG_OF_* to KconfigJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit moves: - CONFIG_OF_CONTROL - SPL_DISABLE_OF_CONTROL from zynq_*_defconfig files into arch/arm/Kconfig "config ARCH_ZYNQ" Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * dts: zynq: Enable spi1 for zc770_xm010 boardJagan Teki2015-07-01-0/+5
| | | | | | | | | | | | | | This patch enables spi1 for zynq zc770_xm010 board dts Signed-off-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_spi: Add fdt support in driverJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * dts: zynq: Add zynq spi controller nodesJagan Teki2015-07-01-0/+24
| | | | | | | | | | | | | | | | | | | | This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * zynq: Kconfig: Enable dm spi and spi_flashJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | | | | Enabled CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH for zynq soc. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* | ARM: UniPhier: add IDs for PH1-Pro5, ProXstream2, PH1-LD6bMasahiro Yamada2015-07-02-0/+9
| | | | | | | | | | | | This prepares for new SoCs support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: UniPhier: re-license device tree files under GPLv2+/X11Masahiro Yamada2015-07-02-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | The current GPL only licensing on the device trees makes it very impractical for other software components licensed under another license. To make it easier to reuse them, the device trees for UniPhier SoCs and boards have already been dual-licensed in Linux. Follow this trend in U-boot too. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: UniPhier: sync device trees with the Linux kernelMasahiro Yamada2015-07-02-12/+178
|/ | | | | | | | | | This makes code diff much easier. Device trees describe hardware attributes, which are independent of software architecture. It generally makes sense to synchronize them beyond software projects. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* dm: ls1021aqds: dts: Use "spi_dataflash" driver instead of "spi_flash_std" ↵Haikun Wang2015-06-30-1/+1
| | | | | | | | | | | | | for DSPI flash The type of DSPI flash on ls1021aqds is AT45DB021, it has specail commands and page-size. Use the special spi flash driver instead of "spi_flash_std" driver. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Tested-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal ↵Ian Campbell2015-06-28-81/+2
| | | | | | | | | | | | | | NAND memory" This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h
* Move default y configs out of arch/board KconfigJoe Hershberger2015-06-25-18/+0
| | | | | | | | | | | | | | | | | | | Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defconfigs... This will cause merge pain if allowed to proliferate. Remove the configs that behave this way from the archs. A few configs still remain, but that is because they only exist as defaults and do not have a proper Kconfig entry. Those appear to be: SPIFLASH DISPLAY_BOARDINFO Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates, drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* siemens,am33x,thuban: rename dxr2 to thubanHeiko Schocher2015-06-19-2/+2
| | | | | | | | Update new naming scheme. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* siemens,am33x,rastaban: add rastaban configHeiko Schocher2015-06-19-0/+5
| | | | | | | | | | rastaban is a draco version with more flash, more RAM and faster CPU. Number of partitions is the same but rootfs partition is different. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Change configuration to prevent DDR reset control from EMIFNishanth Menon2015-06-19-4/+4
| | | | | | | | | | | | | | | | | | | | DRA7/AM57xx devices can be operated in many different configurations. When the SoC is supposed to support a configuration where low power mode state may involve the SoC completely powered off and DDR is in self refresh, SoC EMIF controller should not be the master of the reset signal and an external entity might be in control of things. The default configuration of Linux on TI evms involve not powering off the voltage rails (due to various reasons including reliability concerns) and must not allow DDR reset to be controlled by EMIF. On platforms where external entity might control the reset signal, this configuration will be a "dont care". Fixes: 536d87470869 ("ARM: DRA7: Update DDR IO registers") Tested-by: Keerthy <j-keerthy@ti.com> Acked-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* keystone2: use correct EFUSE_BOOTROM fileds to configure speedVitaly Andrianov2015-06-19-6/+6
| | | | | | | | The get_max_arm_speed() and get_max_dev_speed() used wrong register fields to get the maximum speeds. This commit fixes the bug. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* sun6i: cpu_reset: Do not return from cpu_reset()Hans de Goede2015-06-17-0/+1
| | | | | | | | | | | | Currently on sun6i after a "reset" the prompt returns and the user can even type stuff until the watchdog triggers and does the actual reset. This is somewhat unexpected behavior for the "reset" command, this commit adds an endless loop to wait for the watchdog to trigger so that we do not return to the prompt. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Merge git://git.denx.de/u-boot-usbTom Rini2015-06-15-1/+1
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| * arm: exynos: USB3 PHY base definition for Exynos5 SoCsLukasz Majewski2015-06-08-1/+1
| | | | | | | | | | | | | | | | After that change it would be possible to call samsung_get_base_usb3_phy() function to get proper base address Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-06-15-0/+15
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| * | arm: mvebu: Update CBAR with SOC regs baseKevin Smith2015-06-14-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | SMP-enabled Linux kernels read the CBAR register in CP15 to find the address of the SCU registers. After remapping internal registers, also update the CBAR so the kernel can find them. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Disable L2 cache before enabling d-cacheStefan Roese2015-06-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | L2 cache may still be enabled by the BootROM. We need to first disable it before enabling d-cache support. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
* | | board: add support for Vision System's Baltos Industrial PCYegor Yefremov2015-06-15-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vision Systems's Baltos is based on AM335x SoC from Texas Instruments. This patch adds support such Industrial PCs in mainline u-boot. [ balbi@ti.com: updated original patch to current u-boot ] Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* | | ARM: DRA7: emif: Fix DDR init sequence during warm resetLokesh Vutla2015-06-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after warm reset, emif needs to be configured to bring it back to a known state. So configure EMIF during warm reset. Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | am33xx: Re-enable SW levelling for DDR2Tom Rini2015-06-15-40/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: BeagleBoard-x15: Enable i2c5 clocksLokesh Vutla2015-06-15-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: CPSW: Remove IO delay hackLokesh Vutla2015-06-12-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now all manual mode configurations are done as part of IO delay recalibration sequence, remove the hack done for CPSW. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-12-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-12-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add support for virtual mode configurationLokesh Vutla2015-06-12-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "virtual mode" also programmed. This allows for predefined delay characteristics to be used by the SoC to meet timing characterstics needed for the interface. Provide easy to use macro to do the same. For configuring virtual mode, along with normal pad configuration add the following two steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1 - DELAYMODE filed should be configured with value given in DATA Manual. CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add pinctrl register definitionsLokesh Vutla2015-06-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adopting the pinctrl register definitions from Linux kernel to be consistent. Old definitions will be removed once all the pinctrl data is adapted to new definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-12-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Update DDR IO registersLokesh Vutla2015-06-12-8/+8
| | | | | | | | | | | | | | | | | | | | | Update DDR IO register values. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-12-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Add is_dra72x cpu check definitionLokesh Vutla2015-06-12-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-12-24/+207
|/ / | | | | | | | | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-06-11-20/+49
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| * | dm: usb: tegra: Drop legacy USB codeSimon Glass2015-06-10-3/+0
| | | | | | | | | | | | | | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dts: Disable device tree for SPL on all boardsSimon Glass2015-06-10-0/+15
| | | | | | | | | | | | | | | | | | | | | We plan to enable device tree in SPL by default. Before doing this, explicitly disable it for all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | fdt: arm: Drop device tree paddingSimon Glass2015-06-10-1/+2
| | | | | | | | | | | | | | | | | | | | | The 4KB padding doesn't seem necessary since we don't normally adjust the control device tree file within U-Boot. Also drop the memory table space. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | arm: Allow cleanup_before_linux() without disabling cachesSimon Glass2015-06-10-18/+29
| | | | | | | | | | | | | | | | | | | | | | | | This function is used before jumping to U-Boot, but in that case we don't always want to disable caches. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
| * | dm: tegra: usb: Move USB to driver modelSimon Glass2015-06-10-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow this change was dropped in the various merges. I noticed when I came to turn off the non-driver-model support for Tegra. We need to make this change (and deal with any problems) before going further. Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of http://git.denx.de/u-boot-samsungTom Rini2015-06-10-78/+2
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| * | odroid: dts: cleanup of MAX77686 regulatorsPrzemyslaw Marczak2015-06-10-78/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit cleanup MAX77686 regulator node by: - remove the sub-nodes of unconnected regulators - remove the "regulator-compatible" properties of all regulators This prevents printing init errors for the regulators, with duplicated name strings. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-06-10-0/+1
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| * | | sunxi: Request macpwr gpio before using itHans de Goede2015-06-10-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | This fixes ethernet no longer working on boards which use a gpio to enable the phy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
generated by cgit v1.1 at 2024-11-12 00:13:37 +0000