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| * | | ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R2013-06-10-31/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla2013-06-10-46/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | | ARM: DRA7xx: Update pinmux dataLokesh Vutla2013-06-10-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
| * | | mmc: omap_hsmmc: Update pbias programmingBalaji T K2013-06-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update pbias programming sequence for OMAP5 ES2.0/DRA7 Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: Correct SRAM END addressSricharan R2013-06-10-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: Correct the SYS_CLK to 20MHZSricharan R2013-06-10-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc'sLokesh Vutla2013-06-10-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: OMAP5: DRA7xx: support class 0 optimized voltagesNishanth Menon2013-06-10-12/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA752 now uses AVS Class 0 voltages which are voltages in efuse. This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly. This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: clocks: Fixing i2c_init for PMICLokesh Vutla2013-06-10-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: power Add support for tps659038 PMICLokesh Vutla2013-06-10-1/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: Add control id code for DRA7xxLokesh Vutla2013-06-10-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: OMAP4+: pmic: Make generic bus init and write functionsLokesh Vutla2013-06-10-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.hLokesh Vutla2013-06-10-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: OMAP5: clocks: Do not enable sgx clocksSricharan R2013-06-10-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-06-10-121/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | OMAP5: Fix bug in omap5_es1_prcm structLubomir Popov2013-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly introduced function setup_warmreset_time(), called from within prcm_init(), tries to write to the prm_rsttime OMAP5 register. The struct member holding this register's address is however initialized for OMAP5 ES2.0 only. On ES1.0 devices this uninitialized value causes a second (warm) reset at startup. Add .prm_rsttime address init to the ES1.0 struct. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Acked-by: Tom Rini <trini@ti.com>
| * | | OMAP5: add ABB setup for MPU voltage domainAndrii Tseglytskyi2013-06-10-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch adds a call of abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
| * | | OMAP3+: introduce generic ABB supportAndrii Tseglytskyi2013-06-10-0/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adaptive Body Biasing (ABB) modulates transistor bias voltages dynamically in order to optimize switching speed versus leakage. Adaptive Body-Bias ldos are present for some voltage domains starting with OMAP3630. There are three modes of operation: * Bypass - the default, it just follows the vdd voltage * Foward Body-Bias - applies voltage bias to increase transistor performance at the cost of power. Used to operate safely at high OPPs. * Reverse Body-Bias - applies voltage bias to decrease leakage and save power. Used to save power at lower OPPs. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
| * | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-08-4/+1300
| |\ \ \ | | | |/ | | |/| | | | | | | | | Conflicts: drivers/serial/Makefile
| | * | arm: mxs: Fix vectoring table craftingMarek Vasut2013-06-03-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28 starts from RAM, so the vectoring table at 0x0 is not present. Craft code that will be placed at 0x0 and will redirect interrupt vectoring to proper location of the U-Boot in RAM. Signed-off-by: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | arm: vf610: Add Vybrid VF610 CPU supportAlison Wang2013-06-03-0/+1253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds generic codes to support Freescale's Vybrid VF610 CPU. It aligns Vybrid VF610 platform with i.MX platform. As there are some differences between VF610 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/vf610 directory. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | arm: vf610: Add IOMUX support for Vybrid VF610Alison Wang2013-06-03-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the IOMUX support for Vybrid VF610 platform. There is a little difference for IOMUXC module between VF610 and i.MX platform, the muxmode and pad configuration share one 32bit register on VF610, but they are two independent registers on I.MX platform. A CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference. Signed-off-by: Alison Wang <b18965@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | ARM: tegra: only enable SCU on Tegra20Tom Warren2013-06-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-SPL build of U-Boot on Tegra only runs on a single CPU, and hence there is no need to enable the SCU when running U-Boot. If an SMP OS is booted, and it needs the SCU enabled, it will enable the SCU itself. U-Boot doing so is redundant. The one exception is Tegra20, where an enabled SCU is required for some aspects of PCIe to work correctly. Some Tegra SoCs contain CPUs without a software-controlled SCU. In this case, attempting to turn it on actively causes problems. This is the case for Tegra114. For example, when running Linux, the first (or at least some very early) user-space process will trigger the following kernel message: Unhandled fault: imprecise external abort (0x406) at 0x00000000 This is typically accompanied by that process receving a fatal signal, and exiting. Since this process is usually pid 1, this causes total system boot failure. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, fleshed out description, ported to upstream chipid APIs] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | am33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>Tom Rini2013-06-06-1/+4
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | The location of valid scratch space is dependent on SoC, so move that there. On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR. On am33xx/ti814x we want to use what the ROM defines as "public stack" which is the area after our defined download image space. Correct the comment about and location of CONFIG_SPL_TEXT_BASE. Signed-off-by: Tom Rini <trini@ti.com>
* | | am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.cTom Rini2013-06-05-36/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to call the save_omap_boot_params function on am33xx/ti81xx and other newer TI SoCs, so move the function to boot-common. Only OMAP4+ has the omap_hw_init_context function so add ifdefs to not call it on am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx boards. Reviewed-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | am33xx: Correct NON_SECURE_SRAM_START/ENDTom Rini2013-06-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Sricharan's cleanup of the boot parameter saving code, we did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a problem that the address was pointing to the middle of our running SPL. Correct to point to the base location of the download image area. Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being used. As part of correcting these tests, make use of the fact that we've always been placing our stack outside of the download image area (which is fine, once the downloaded image is run, ROM is gone) so correct the max size test to be the ROM defined top of the download area to where we link/load at. Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v2: - Fix typo noted by Peter Korsgaard
* | | omap-common/hwinit-common.c: Mark omap_rev_string as staticTom Rini2013-06-04-1/+1
| | | | | | | | | | | | | | | | | | Only called in this file, mark as static. Signed-off-by: Tom Rini <trini@ti.com>
* | | arm: factorize relocate_code routineAlbert ARIBAUD2013-05-30-992/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all relocate_code routines from ARM start.S files with a single instance in file arch/arm/lib/relocate.S. For PXA, this requires moving the dcache unlocking code from within relocate_code into c_runtime_cpu_setup. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | arm: do not compile relocate_code() for SPL buildsAlbert ARIBAUD2013-05-30-81/+55
| | | | | | | | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-124/+126
|\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * | | arm: Use image_setup_linux() instead of local codeSimon Glass2013-05-14-56/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the common FDT setup function that is now available in image. Move the FDT-specific code to a new bootm-fdt.c and remove unused headers from bootm.c. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | arm: Refactor bootm to reduce #ifdefsSimon Glass2013-05-14-68/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With fewer #ifdefs the code is more readable and more of the code is compiled for all boards. Add defines in the header file to control what features are enabled, and then use if() instead of #ifdef. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL buildAxel Lin2013-05-28-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_critAxel Lin2013-05-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_init_crit() can be skipped, but the code is still enabled requiring a platform to supply lowlevel_init(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | ARM: tegra: support SKU 7 of Tegra20Stephen Warren2013-05-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make U-Boot aware of the Tegra20 SKU 7, and treat it identically to any other Tegra20. My Whistler board has a SoC with this SKU. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | ARM: tegra: support SKU 1 of Tegra114Stephen Warren2013-05-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make U-Boot aware of the Tegra114 SKU 1, and treat it identically to any other Tegra114. This value is used on (at least some) Dalmore boards with a production rather than engineering chip. Such boards are in the hands of some partners who want to use upstream U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | Tegra: clk: always use find_best_divider() for periph clocksAllen Martin2013-05-28-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like "sf" where the user can pass a clock speed on the command line or "sspi" where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | arm: Enable -ffunction-sections / -fdata-sections / --gc-sectionsTom Rini2013-05-23-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While other architectures have enabled these gcc / ld options for some time on U-Boot itself, ARM has only been doing this on SPL. Enable this on full U-Boot as well now. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@ti.com>
* | | | ARM: atmel: add sama5d3xek supportBo Shen2013-05-21-0/+947
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sama5d3xek support with following feature - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector - boot from SPI flash support - boot from SD card support - LCD support - EMAC support - USB OHCI support Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | | ARM: at91: add Atmel sama5d3 SoC new pmc registerBo Shen2013-05-21-0/+23
| |_|/ |/| | | | | | | | | | | | | | | | | Add Atmel sama5d3 SoC new pmc register Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: enable mci support for at91sam9g20ek.Wu, Josh2013-05-12-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: add at91sam9n12ek board supportWu, Josh2013-05-12-2/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for following features: - nand boot, with PMECC 2bit ECC for 512 bytes sector - SPI flash boot - SD card boot - LCD support Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix -Wimplicit-function-declaration for at91_lcd_hw_init()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: add at91sam9n12 register definitionWu, Josh2013-05-12-8/+32
| |/ |/| | | | | | | | | | | | | Since at91sam9n12 is a subset of at91sam9x5, so put all at91sam9n12 definitions in at91sam9x5 head file. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-206/+371
|\ \
| * | ARM: OMAP: Add arch_cpu_init functionSRICHARAN R2013-05-10-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The boot parameters passed from SPL to UBOOT must be saved as a part of uboot's gd data as early as possible, before we will inadvertently overwrite it. So adding a arch_cpu_init for the required Socs to save it. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: OMAP: Cleanup boot parameters usageSRICHARAN R2013-05-10-83/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: OMAP: Correct save_boot_params and replace with 'C' functionSRICHARAN R2013-05-10-7/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines commonSRICHARAN R2013-05-10-33/+24
| | | | | | | | | | | | | | | | | | | | | | | | These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | ARM: OMAP: Make omap_boot_parameters common across socsSRICHARAN R2013-05-10-72/+49
| | | | | | | | | | | | | | | | | | | | | | | | omap_boot_parameters is same and defined for each soc. So move this to a common place to reuse it across socs. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | am33xx: Fix warning with CONFIG_DISPLAY_CPUINFOTom Rini2013-05-10-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | The arm_freq and ddr_freq variables are unused, so remove. Fixup whitespace slightly while in here. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-11-12 19:56:46 +0000