| Commit message (Collapse) | Author | Age | Lines |
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This is needed to correctly apply the new Jetson TK1 pinmux config.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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When the CPU is in non-secure (NS) mode (when running U-Boot under a
secure monitor), certain actions cannot be taken, since they would need
to write to secure-only registers. One example is configuring the ARM
architectural timer's CNTFRQ register.
We could support this in one of two ways:
1) Compile twice, once for secure mode (in which case anything goes) and
once for non-secure mode (in which case certain actions are disabled).
This complicates things, since everyone needs to keep track of
different U-Boot binaries for different situations.
2) Detect NS mode at run-time, and optionally skip any impossible actions.
This has the advantage of a single U-Boot binary working in all cases.
(2) is not possible on ARM in general, since there's no architectural way
to detect secure-vs-non-secure. However, there is a Tegra-specific way to
detect this.
This patches uses that feature to detect secure vs. NS mode on Tegra, and
uses that to:
* Skip the ARM arch timer initialization.
* Set/clear an environment variable so that boot scripts can take
different action depending on which mode the CPU is in. This might be
something like:
if CPU is secure:
load secure monitor code into RAM.
boot secure monitor.
secure monitor will restart (a new copy of) U-Boot in NS mode.
else:
execute normal boot process
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Some systems have so much RAM that the end of RAM is beyond 4GB. An
example would be a Tegra124 system (where RAM starts at 2GB physical)
that has more than 2GB of RAM.
In this case, we want gd->ram_size to represent the actual RAM size, so
that the actual RAM size is passed to the OS. This is useful if the OS
implements LPAE, and can actually use the "extra" RAM.
However, we can't use get_ram_size() to verify the actual amount of RAM
present on such systems, since some of the RAM can't be accesses, which
confuses that function. Avoid calling get_ram_size() when the RAM size
is too large for it to work correctly. It's never actually needed anyway,
since there's no reason for the BCT to report the wrong RAM size.
In systems with >=4GB RAM, we still need to clip the reported RAM size
since U-Boot uses a 32-bit variable to represent the RAM size in bytes.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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size_mb is used to hold a value that's sometimes KB, sometimes MB,
and sometimes bytes. Use separate correctly named variables to avoid
confusion here. Also fix indentation of a conditional statement.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined,
smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr(
_smp_pen), before code is relocated to secure ram.
So need relocation to secure ram before enable secondary cores.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
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ED Mini V2 is based on Orion 5x which boots at fixed
address 0xFFFF0000 in NOR Flash. Place SPL there, and
switch U-Boot from .bin to .img format, stored in
NOR Flash at 0xFFF90000.
Note: this patch was tested on HW and works, i.e.
it boots U-Boot properly, but SPL console output
currently does not appear, due to GD being trashed
by arch/arm/lib/spl.c. This trashing is soon to be
removed, and then ED Mini V2 SPL console output will
become visible.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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If we don't know the relocation address, the raw values are not very useful.
Show the pre-relocation values as well as these can be looked up in
System.map, etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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This patch adds basic constructs in the ARMv8 u-boot code
to handle and apply Cortex-A57 specific erratas.
As and example, the framework showcases how erratas 833069, 826974
and 828024 can be handled and applied.
Later on this framework can be extended to include other
erratas.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
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While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.
The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.
Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.
This makes the Juno platform start U-Boot properly.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The way the PSCI DT update happens currently means we pull in
<asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in
<asm/io.h> for some non-PSCI related things that header needs to deal
with.
To fix this, we rework the hook slightly. A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large. So rename the
current hook to psci_update_dt(), move the prototype to <asm/psci.h> and
add an #ifdef that will make re-use later easier.
Reported-by: York Sun <yorksun@freescale.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: York Sun <yorksun@freescale.com>
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For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performance. This is able
thanks to the ARM multiple register instructions.
Unfortunatelly the relocation is done without the cache enabled,
so it takes some time, but zeroing the BSS memory takes much more
longer, especially for the configs with big static buffers.
A quick test confirms, that the boot time improvement after using
the arch memcpy for relocation has no significant meaning.
The same test confirms that enable the memset for zeroing BSS,
reduces the boot time.
So this patch enables the arch memset for zeroing the BSS after
the relocation process. For ARM boards, this can be enabled
in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'.
This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1384ms - before this change
- ~888ms - after this change
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
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Import DTS for Arria V development kit and enable support
for DT. The DT is imported from Linux 3.19-rc1 as of commit
97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
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Import DTS for Cyclone V development kit and enable support
for DT. The DT is imported from Linux 3.19-rc1 as of commit
97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
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Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
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esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's are enabled.
Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw <hamming|bch8>
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
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This patch extends OMAP3 support for AM/DM37xx and
introduces the AM3703-based Quipos Cairo board.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Reviewed-by: Simon Glass <sjg@chromium.org>
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According to table 2-3 on page 87 of Marvell's latest PXA270
Specification Update Rev. I from 2010.04.19 [1] there exists a breed of
chips with a new CPU ID for PXA270M A1 stepping which our latest
Colibri PXA270 V2.4A modules actually have assembled. This patch helps
in correctly identifying those chips upon boot as well which then looks
as follows:
CPU: Marvell PXA27xM rev. A1
[1] http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf
Acked-by: Marek Vasut <marex@denx.de>
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commit d9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb sets
get_reset_cause() as static, but this conflicts with mx5
where its prototype is in sys_proto.h.
Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco,
factorizing the call for this board.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
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Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.
During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process, is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.
Commands added
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dek_blob - encapsulating DEK as a cryptgraphic blob
Commands Syntax
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dek_blob src dst len
Encapsulate and create blob of a len-bits DEK at
address src and store the result at address dst.
Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com>
Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
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Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx35
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX35 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
This allows mx35 to boot again.
Cc: Sebastian Priebe <sebastian.priebe@cadcon.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
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Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx31
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX31 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
This allows mx31 to boot again.
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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The WaRP Board is a Wearable Reference Plaform. The board features:
- Freescale i.MX6 SoloLite processor with 512MB of RAM
- Freescale FXOS8700CQ 6-axis Xtrinsic sensor
- Freescale Kinetis KL16 MCU
- Freescale Xtrinsic MMA955xL intelligent motion sensing platform
The board implements a hybrid architecture to address the evolving
needs of the wearables market. The platform consists of a main board
and an example daughtercard with the ability to add additional
daughtercards for different usage models.
For more information about the project, visit:
http://www.warpboard.org/
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
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This adds the DATA[4-7] and RST pin definitions.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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A few pad settings are I2C1
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
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There are three wdogs for i.MX 6SoloX. Add wdog3 support
in function imx_set_wdog_powerdown.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should
be disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f(). Adjust the
code paths in these cases to be correct. In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment). In these cases switch to CONFIG_SPL_STACK_R. In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM
Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point into SDRAM. They then set up SDRAM very early, before board_init_f(),
so that the larger stack can be used.
This is an abuse of lowlevel_init(). That function should only be used for
essential start-up code which cannot be delayed. An example of a valid use is
when only part of the SPL code is visible/executable, and the SoC must be set
up so that board_init_f() can be reached. It should not be used for SDRAM
init, console init, etc.
Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new
address before board_init_r() is called in SPL.
The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README.
Signed-off-by: Simon Glass <sjg@chromium.org>
For version 1:
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Use the full driver model GPIO and serial drivers in SPL now that these are
supported. Since device tree is not available they will use platform data.
Remove the special SPL GPIO function as it is no longer needed.
This is all in one commit to maintain bisectability.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.
As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver model in SPL and allow the stragglers
to catch up.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).
There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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With a389531 we now call readl() from this file so add <asm/io.h> so
that we have a prototype for the function.
Signed-off-by: Tom Rini <trini@konsulko.com>
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It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).
This also provides a big cleanup of the L2 cache init code avoiding
some duplication. The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
time) and left resident in iRAM for the kernel to use when bringing
up additional CPUs. It used configure_l2_ctlr() and
configure_l2_actlr() when it detected it was on an A15. This was
needed (despite the L2 cache registers being shared among all A15s)
because we might have been the first man in after the whole A15
cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
time. Strangely this called configure_l2_ctlr() but not
configure_l2_actlr() which was almost certainly wrong. Given that
we'll call both (see next bullet) later in the boot process it
didn't matter for normal boot, but I guess this is how L2 cache
settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
This should happen at boot time (normally in the SPL except for USB
boot where it happens in main U-Boot).
Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time. For resume time we'd get it
anyway when the 2nd A15 core came up.
Let's make this a whole lot simpler. Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.
Intended net effects of this change (other than cleanup):
* Timings go from before:
data: 0 cycle setup, 3 cycles (0x2) latency
tag: 0 cycle setup, 3 cycles (0x2) latency
after:
data: 1 cycle setup, 4 cycles (0x3) latency
tag: 1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.
One note is that we're still relying on luck to keep low_power_start()
working. The compiler is being nice and not storing anything on the
stack.
Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL. The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
(after it has turned the L2 cache off). This is why the functions
are in a header file instead of lowlevel_init.c.
* Have the kernel save the L2 cache settings of the boot CPU and apply
them to all other CPUs. We get a little lucky here because the old
code was using "|=" to modify the registers and all of the bits that
it's setting are also present in the new settings (!). That means
that when the 2nd CPU in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.
This issue is fixed by replacing the "mov pc" instruction with a "bx"
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.
Logic of the workaround:
Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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