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* i.mx: iomux-v3.h: move to imx-common include directoryTroy Kisky2012-07-31-2/+2
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* iomux-v3: remove include of mx6x_pins.hTroy Kisky2012-07-31-1/+0
| | | | | | | This include is not needed. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
* ARM1136: Fix cache range checksBenoît Thébaudeau2012-07-21-3/+3
| | | | | | | | | | | | | | bad_cache_range actually returned true if the range was OK, but it was used according to its name, which resulted in all valid dcache range invalidate/flush operations being dropped. Hence, most DMA transfers resulted in garbage data. This patch renames this function according to what it does, and it fixes the interpretation of its return value by other functions. The chosen naming is the same as for ARM926EJ-S in order to be consistent. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: Make pad name macro consistent with the datasheetAshok2012-07-20-2/+2
| | | | | | | | Use the same name as defined in the datasheet. DSP_CLK -> DISP_CLK Signed-off-by: Ashok Kumar Reddy Kourla <ashokkourla2000@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependencyFabio Estevam2012-07-20-2/+8
| | | | | | | | | | | | Create a weak-aliased arch_cpu_init, so that we can get rid of CONFIG_ARCH_CPU_INIT and always call arch_cpu_init. This way we do not need to define CONFIG_ARCH_CPU_INIT in every board file, since arch_cpu_init() is supposed to handle common CPU level code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* arm: armv7: add compile option -mno-unaligned-access if availableTetsuyuki Kobayashi2012-07-20-0/+2
| | | | | | | | | | Recent compiler generates unaligned memory access in armv7 default. But current U-Boot does not allow unaligned memory access, so it causes data abort exception. This patch add compile option "-mno-unaligned-access" if it is available. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Tested-by: Gary Thomas <gary@mlbassoc.com>
* arm: Fix to mistake clean the memory spaceZhong Hongbo2012-07-20-40/+65
| | | | | | | | | | | In currently, when __bss_start is equal to __bss_end__, The bss loop will clear all the things in memory space. But just only when __bss_end__ greater than __bss_start__, we do the clear bss section operation. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'next' of git://git.denx.de/u-boot-videoWolfgang Denk2012-07-18-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot-video: ipu_common: Add ldb_clk for use in parenting the pixel clock ipu_common: Do not hardcode the ipu_clk frequency ipu_common: Rename MXC_CCM_BASE ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53 ipu_common: Only apply the erratum to MX51 video: Rename CONFIG_VIDEO_MX5 mx6: Allow mx6 to access the IPUv3 registers common lcd: minor coding style changes Signed-off-by: Wolfgang Denk <wd@denx.de>
| * mx6: Allow mx6 to access the IPUv3 registersFabio Estevam2012-07-10-2/+3
| | | | | | | | | | | | Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mxc_i2c: specify i2c base address in config fileTroy Kisky2012-07-11-1/+8
|/ | | | | | | | | The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd and mx53loco. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-07-10-2/+96
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: tegra: define fdt_load/fdt_high variables tegra: enable bootz command tegra: usb: Fix device enumeration problem of USB1 tegra: trimslice: set up serial flash pinmux tegra: add pin_mux_spi() board initialization function tegra: add GMC/GMD funcmux entry for SFLASH tegra: bootcmd: start USB only when needed tegra: bootcmd enhancements tegra: add enterrcm command tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG Add env vars describing U-Boot target board tegra: usb: fix wrong error check tegra: add ULPI on USB2 funcmux entry tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches tegra: Add Tamonten Evaluation Carrier support tegra: Use SD write-protect GPIO on Tamonten tegra: Implement gpio_early_init() on Tamonten tegra: Allow boards to perform early GPIO setup tegra: plutux: Add device tree support tegra: medcom: Add device tree support tegra: Rework Tamonten support beagle: add eeprom expansion board info for bct brettl4 Signed-off-by: Wolfgang Denk <wd@denx.de>
| * tegra: usb: Fix device enumeration problem of USB1Jim Lin2012-07-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A known hardware issue of USB1 port where bit 1 (connect status change) of PORTSC register will be set after issuing Port Reset (like "usb reset" in u-boot command line). This will be treated as an error and stops later device enumeration. Therefore we clear that bit after Port Reset in order to proceed later device enumeration. Signed-off-by: Jim Lin <jilin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add GMC/GMD funcmux entry for SFLASHStephen Warren2012-07-09-0/+13
| | | | | | | | | | | | | | This is used on TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add enterrcm commandStephen Warren2012-07-09-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's boot ROM supports a mode whereby code may be downloaded and flash programmed over a USB connection. On dev boards, this is typically entered by holding down a "force recovery" button and resetting the CPU. However, not all boards have such a button (one example is the Compulab Trimslice), so a method to enter RCM from software is useful. This change implements the command "enterrcm" to do this, and enables it for all Tegra boards by default. Even on boards other than Trimslice, controlling this over a UART may be useful, e.g. to allow simple remote control without the need for mechanical button actuators, or hooking up relays/... to the button. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: usb: fix wrong error checkLucas Stach2012-07-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | loop_count runs down from 10000, so the correct condition to error out is ==0. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren.nvidia@gmail.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add ULPI on USB2 funcmux entryLucas Stach2012-07-09-1/+15
| | | | | | | | | | | | | | | | | | | | | | This is needed as a prerequisite for Tegra USB ULPI support within U-Boot. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | EXYNOS: Fix USB compiler warningRajeshwari Shinde2012-07-10-1/+0
| | | | | | | | | | | | | | Fixed the compiler warning message. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-07-09-7/+684
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250 EXYNOS5: USB: Fix incorrect USB base addresses EXYNOS: Add power Enable/Disable for USB-EHCI USB: EXYNOS: Set USB 2.0 HOST Link mode EXYNOS5: Add structure for PMU registers EXYNOS5: Fix system register structure USB: EXYNOS: Incorporate EHCI review comments Signed-off-by: Wolfgang Denk <wd@denx.de>
| * EXYNOS5: USB: Fix incorrect USB base addressesRajeshwari Shinde2012-07-09-2/+2
| | | | | | | | | | | | | | | | | | This patch corrects the base addresses for USB_PHY and USB_OTG. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS: Add power Enable/Disable for USB-EHCIRajeshwari Shinde2012-07-09-0/+26
| | | | | | | | | | | | | | | | | | This patch adds functions to enable/disable the power of USB host controller for EXYNOS5. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
| * USB: EXYNOS: Set USB 2.0 HOST Link modeRajeshwari Shinde2012-07-09-0/+25
| | | | | | | | | | | | | | This patch adds a function to set usb host mode to USB 2.0 HOST Link for EXYNOS5 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
| * EXYNOS5: Add structure for PMU registersRajeshwari Shinde2012-07-09-0/+622
| | | | | | | | | | | | | | | | This patch adds power mananagement registers structure for exynos5 SoC. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5: Fix system register structureRajeshwari Shinde2012-07-09-0/+1
| | | | | | | | | | | | | | | | | | This patch corrects the SYSREG structure. We have removed the sysreg.h added in the previous patchset version as the sysreg structure is already defined in system.h. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * USB: EXYNOS: Incorporate EHCI review commentsRajeshwari Shinde2012-07-09-5/+8
| | | | | | | | | | | | | | This patch incorates the review comments given by Minkyu Kang for EHCI support on EXYNOS Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* | Revert "arm: bugfix: save_boot_params_default accesses uninitalized stack ↵Wolfgang Denk2012-07-09-7/+1
|/ | | | | | | | | | | when -O0" This reverts commit fa042186b932e9b9ee9a2fd8a04a3acf7c70d224. It causes build warnings like this: cpu.c:48:1: warning: -fstack-usage not supported for this target [enabled by default] Signed-off-by: Wolfgang Denk <wd@denx.de>
* ARM: cache: Move the cp15 CR register read before flushing the cache.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c int cleanup_before_linux(void) { ... ... dcache_disable(); v7_outer_cache_disable(); invalidate_dcache_all(); } 1) invalidate_dcache_all call expects that all the caches has been flushed, invalidated and there are no dirty entries prior to its execution. In the above sequence dcache_disable() flushes, invalidates the caches and turns off the mmu. But after it cleanups the cache and before the mmu is disabled there is a cp_delay() function which has STR instruction. On certain cores like the cortex-a15, cache hit and a write can happen to a cache line even when the dcache is disabled. So the above mentioned STR instruction creates a dirty entry after cleaning. The mmu gets disabled after this. 2) invalidate_dcache_all invalidates the cache lines. Again on cores like cortex-a15, invalidate instruction flushes the dirty line as well. So some times the dirty line from sequence 1 can corrupt the memory resulting in a crash. Fixing this by moving the get_cr() and cp_delay() calls before cleaning up the cache, thus avoiding the dirty entry. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: introduce arch_early_init_r()Fabio Estevam2012-07-07-0/+5
| | | | | | | Introduce arch_early_init_r() function, which can be useful for doing early initialization after relocation has happened. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* ARM: mx28: Remove CONFIG_ARCH_CPU_INITFabio Estevam2012-07-07-2/+0
| | | | | | | | | No need to define CONFIG_ARCH_CPU_INIT. All mx28 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* No need to define CONFIG_ARCH_CPU_INIT.Fabio Estevam2012-07-07-2/+0
| | | | | | | All mx6 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* SPL: ARM: spear: Add SPL support for SPEAr600 platformStefan Roese2012-07-07-27/+1740
| | | | | | | | | | | | This patch adds SPL support for SPEAr600. Currently only SNOR (Serial NOR) flash support is included. Other boot devices (NAND, MMC, USB ...) may be added with later patches. Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
* arm: Don't use printf() in SPL buildsSimon Glass2012-07-07-1/+2
| | | | | | | | | | | | | | raise() likes to call printf() if it is available, but in SPL builds it either is not available, or adds a large chunk to the resulting image size. So don't call it even if it is available. This change reduces SPL size from 10KB to 6.3KB on hawkboard, for example, using generic relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
* GPIO: Add SPEAr GPIO driverStefan Roese2012-07-07-0/+40
| | | | | | Tested on x600 (SPEAr600). Signed-off-by: Stefan Roese <sr@denx.de>
* cleanup/SPEAr: Remove unnecessary parenthesisAmit Virdi2012-07-07-2/+2
| | | | | | | | | In SPEAr configuration files, unnecessary paranthesis are used in some \#defines. Remove them as they serve no purpose Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: Correct SoC ID offset in misc configuration spaceShiraz Hashim2012-07-07-1/+1
| | | | | | | | | | SoC Core ID offset is 0x30 in miscellaneous configuration address space. It was wrongly mentioned as periph2 clk enable. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: explicitly select clk src for UARTShiraz Hashim2012-07-07-1/+8
| | | | | | | | | | UART in u-boot intends to run on 48MHz clock supplied by USB PLL. Explicitly select the intended clock source. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: Add basic arch related support for SPEAr SoCsVipin KUMAR2012-07-07-1/+91
| | | | | | | | | | | Earlier, architecture specific init code was mixed with board initialization code in board/spear/... This patch updates architecture support for SPEAr in latest u-boot and prints the SoC information. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: Add macb driver support for spear310 and spear320Vipin KUMAR2012-07-07-0/+34
| | | | | | | | | | | SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The driver for this device is already supported by u-boot, so configuring board configuration file and defining base addresses etc to make use of the common driver Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: Configure network support for spear SoCsVipin KUMAR2012-07-07-0/+1
| | | | | | Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: Eliminate dependency on Xloader tableAmit Virdi2012-07-07-74/+0
| | | | | | | | | | Xloader table was used primarily to inform u-boot about the DDR size. However, now the ddr size is calculated at runtime which eliminates any need for the Xloader table. So removing this unnecessary code. Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* st_smi: Add support for SPEAr SMI driverVipin KUMAR2012-07-07-115/+0
| | | | | | | | | | | | | | SMI is the serial memory interface controller provided by ST. Earlier, a driver exists in the u-boot source code for the SMI IP. However, it was specific to spear platforms. This commit converts the same driver to a more generic driver. As a result, the driver files are renamed to st_smi.c and st_smi.h and moved into drivers/mtd folder for reusability by other platforms using smi controller peripheral. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mtd/NAND: Remove obsolete SPEAr specific NAND driversVipin KUMAR2012-07-07-57/+0
| | | | | | | | | | | Since, SPEAr platform uses generic FSMC driver now, so spear specific files drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* SPEAr: Configure FSMC driver for NAND interfaceVipin KUMAR2012-07-07-4/+4
| | | | | | | | | | | Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0Tetsuyuki Kobayashi2012-07-07-1/+7
| | | | | | | | save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: Move USB clocks to essential group.SRICHARAN R2012-07-07-9/+7
| | | | | | | | | USB clocks will be required for fastboot, tftp related functionalities. Move these clocks to essential group inorder to have the functionality working when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4/5: Move gpmc clocks to essential group.SRICHARAN R2012-07-07-2/+2
| | | | | | | | | | GPMC clocks are currently getting enabled as a part non-essential clocks. This will be required during NOR boot. Move this to essential group to keep the functionality, when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4+: Move external phy initialisations to arch specific place.SRICHARAN R2012-07-07-27/+39
| | | | | | | | | | The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* omap4: Use a smaller M,N couple for IVA DPLLSebastien Jan2012-07-07-1/+1
| | | | | | | | | | This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan <s-jan@ti.com>
* omap: am33xx: accomodate input clocks other than 24 MhzSteve Sakoman2012-07-07-5/+5
| | | | | | | | | The PLL setup values currently assume a 24 Mhz input clock. This patch uses V_OSCK from the board config file to support boards with different input clock rates. Signed-off-by: Steve Sakoman <steve@sakoman.com>
* omap: emif: fix bug in manufacturer code testSteve Sakoman2012-07-07-1/+1
| | | | | | | Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so Micron memory will not be detected! Signed-off-by: Steve Sakoman <steve@sakoman.com>
* omap: emif: deal with rams that return duplicate mr data on all byte lanesSteve Sakoman2012-07-07-1/+6
| | | | | | | | | | Some rams (Micron for example) return duplicate mr data on all byte lanes. Users of the get_mr function currently don't deal with this duplicated data gracefully. This patch detects the duplicated data and returns only the expected 8 bit mr data. Signed-off-by: Steve Sakoman <steve@sakoman.com>
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