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* zynq: Fix elf header generationMichal Simek2014-02-13-0/+99
| | | | | | | | | | | | This patch is here because of: "arm: keep all sections in ELF file" (sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7) Our tools expect to have elf with only LOAD header. Without this fix also PHDR, INTERP and DYNAMIC headers are available in ELF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: bcm2835: config.mk isn't neededStephen Warren2014-02-13-19/+0
| | | | | | | | | | | | | | | | | | The entries in config.mk were needed so that U-Boot could be built with an old version of the Raspberry Pi Foundation's toolchain. Without them, the build would error out with: ...-ld: error: .../libgcc.a(_bswapsi2.o) uses VFP register arguments, u-boot does not However, none of the 3 toolchains in the latest version of their tools.git, nor the Ubuntu/Linaro ARM compilers in at least Ubuntu Quantal or Saucy, need these options set in order to compile a working U-Boot. Hence, remove the options for simplicity. Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-13-256/+145
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| * exynos: clock: use the clear and set bits macros.Inha Song2014-02-10-65/+20
| | | | | | | | | | | | | | | | | | Use setbits/clrbits macro instead of readl/writel function. (Suggested by Wolfgang) Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos: clock: fixed that cfg is set to wrong value.Inha Song2014-02-10-0/+3
| | | | | | | | | | | | | | | | | | This patch fixed that cfg value is set to wrong value. Because it didn't read the related register. Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm:s5pc110: add cpu revisionPiotr Wilczek2014-02-07-0/+7
| | | | | | | | | | | | | | | | This patch adds s5p_cpu_rev. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm:exynos: add cpu revisionPiotr Wilczek2014-02-07-2/+6
| | | | | | | | | | | | | | | | This patch enables to read cpu revision on Exynos CPU. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos: pinmux: remove unnecessary routineMinkyu Kang2014-02-05-6/+1
| | | | | | | | | | | | | | | | | | | | Because of the list of peripherals is not sequential, such a routine does not check for valid correctly. Error check will be done when call the exynos_pinmux_config function. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
| * exynos: pinmux: remove unnecessary defineMinkyu Kang2014-02-05-2/+1
| | | | | | | | | | | | The value of PERIPH_ID_COUNT was wrong, and unnecessary. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos: pinmux: sort the list of peripheralsMinkyu Kang2014-02-05-1/+1
| | | | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Rajehswari Shinde <rajeshwari.s@samsung.com>
| * s5p: gpio: change gpio coding method for s5p gpio.Przemyslaw Marczak2014-02-03-183/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | Old s5p gpio coding method was not clean and was not working properly for all parts and banks. New method is clean and easy to extend. Gpio coding mask: 0x000000ff - pin number 0x00ffff00 - bank offset 0xff000000 - part number Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | ARM: tegra: add DT files for Tegra124 and Venice2Tom Warren2014-02-03-0/+250
| | | | | | | | | | | | | | | | | | | | These are fairly complete, and near-clones of Tegra114 Venice, with an additional I2C port, and MMC address changes for Tegra124. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: add common (shared) CPU filesTom Warren2014-02-03-12/+24
| | | | | | | | | | | | | | | | | | These files are used by both SPL and main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add CPU (armv7) files for Tegra124Tom Warren2014-02-03-0/+1651
| | | | | | | | | | | | | | | | | | | | | | These files are for code that runs on the CPU (A15) on Tegra124 boards. At this time, there is no A15-specific code here. The warmboot/LP0 files aren't included as that code hasn't been ported yet. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124Tom Warren2014-02-03-2/+318
| | | | | | | | | | | | | | | | | | | | This provides SPL support for Tegra124 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: add/edit headers for Tegra124Tom Warren2014-02-03-28/+2419
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These headers define the Tegra124 hardware. Add them to the usual place. Add Tegra124 chip ID/SKU ID definitions to common headers. There's no real HW change on Tegra124 for 90% of the toys, so it might make sense for a future patch to unify some of the content of these files in a common location. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix a typo in the tegra114.dtsiStephen Warren2014-02-03-1/+1
| | | | | | | | | | | | | | | | | | The reg property for node spi@7000d800 was wrong. Fix it to match the HW. This change was verified against the Linux kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: remove a conditional for CSITE rateStephen Warren2014-02-03-14/+6
| | | | | | | | | | | | | | | | | | | | | | There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: enable PLLX only once it's been fully configuredStephen Warren2014-02-03-4/+9
| | | | | | | | | | | | | | | | | | This programming sequence is correct per Jimmy Zhang, and makes sense too! Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: pass just partition ID to power_partition()Stephen Warren2014-02-03-18/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Pass just the partition ID to power_partition(), rather than also passing the partition's status register mask too. This makes it simpler to get call-sites correct, since they don't need to pass two different values that define the same thing and must match. Consequently, we can remove the mask definitions from pmc.h. Suggested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: misc cleanups triggered by Tegra124 reviewStephen Warren2014-02-03-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | Use a named constant for the PLL lock bit in enable_cpu_clocks(). Construct the complete value of pmc_pwrgate_toggle, rather than doing a read-modify-write; the register is simple enough and doesn't need to maintain state between operations. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: don't exceed AVP limits when configuring PLLPJimmy Zhang2014-02-03-87/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the Tegra TRM, the system clock (which is the AVP clock) can run up to 275MHz. On power on, the default sytem clock source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 408MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP, and then switch back to PLLP_OUT4, which has an appropriate divider configured, after PLLP has been configured Implement this logic in new function tegra30_set_up_pllp(), which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP clock switching. Remove the duplicate PLLP setup from pllx_set_rate() and adjust_pllp_out_freqs(). Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> [swarren, significantly refactored the change] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: amend pmc.h for Tegra114+Stephen Warren2014-02-03-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra114 and later's PMC module removes the pwrgate_timer_on register and replaces it with a clamp_status register. Adjust pmc.h to reflect this, and update any code affected by the change. The cpu.c change in this patch was extracted from a much larger patch by Jimmy Zhang. The pmc.h change was written from scratch, but inspired by related changes made by Tom Warren. There could well be other differences in the PMC register set for chips after Tegra20/30. However, they don't affect the code in U-Boot at present, so I haven't attempted an exhaustive update of pmc.h. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: implement MASK_BITS_31_29Tom Warren2014-02-03-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Some clock sources have 3-bit muxes in bits 31:29. Implement core support for this mux field. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: MASK_BITS_ no longer needs specific valuesStephen Warren2014-02-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all code that sets or interprets MASK_BITS_* now uses the enums to define/compare the values, there is no need for MASK_BITS_* to have a specific integer value. In fact, having a specific integer value may encourage people to hard-code those values, or interpret the values in incorrect ways. As such, remove the logic that assigns a specific value to the enum values in order to make it completely clear that it's just an enum, not something that directly represents some integer value. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: use MASK_BITS_* macros everywhereStephen Warren2014-02-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all code that set or interpreted "mux_bits" was using the named macros, but rather some was simply using hard-coded integer constants. This makes it hard to determine which pieces of code are affected by changes to those constants. Replace the integer constants with the equivalent macro definitions so that everything is nicely tied together. Note that I'm not convinced all the code was using the correct integer constants, and hence I'm not convinced that all the code is now using the desired macros. However, this change is a purely mechanical replacement and should have no functional change. Fixing any bugs will come later, separately. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: rename OUT_CLK_SOURCE_*Stephen Warren2014-02-03-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OUT_CLK_SOURCE_ are currently named after the number of bits the mask they represent includes. However, bit count is not the only possible variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to more completely describe exactly what they represent, without having to go look up the definitions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28Stephen Warren2014-02-03-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only place where the MASK_BITS_* values are used is in adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28, new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK, i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually implemented. Note that no Tegra clock register actually uses all of bits 31:28 as the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in those cases, nothing is stored in the bits above the mux field, so it's safe to pretend that the mux field extends all the way to the end of the register. As such, the U-Boot clock driver is currently a bit lazy, and doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps them all together and pretends they're all 31:28. This patch doesn't cause this issue; it was pre-existing. Hopefully, future patches will clean this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: deduplicate MASK_BITS_xxx clock mux enumTom Warren2014-02-03-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The enum used to define the set of register bits used to represent a clock's input mux, MUX_BITS_*, is defined separately for each SoC at present. Move this definition to a common location to ease fixing up some issues with the definition, and the code that uses it. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: accept any SKU ID for most chipsStephen Warren2014-02-03-0/+2
|/ | | | | | | | | | | | | | | | | | For Tegra20, the SKU ID actually impacts how U-Boot programs the chip, and hence we need to explicitly know about each and every SKU ID in order to operate correctly. However, for Tegra30/114, this isn't the case. Rather than forcing each new user with a different SKU to manually add their SKU ID into the code, simply accept any SKU ID. If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll need to undo this, or make the default case map to conservative defaults, but for now it's likely the path to least support cost. Reported-by: Olof Johansson <olof@lixom.net> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-29-248/+40
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| * DRA7: add ABB setup for MPU voltage domainNishanth Menon2014-01-24-3/+20
| | | | | | | | | | | | | | | | | | Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * DRA7: Add support for ES1.1 silicon ID codeNishanth Menon2014-01-24-3/+13
| | | | | | | | | | | | | | | | ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support for ES1.1 IDCODE change. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * ARM: AM335x: Enable DDR dynamic IO power downSatyanarayana, Sandhya2014-01-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables dynamically powering down the IO receiver when not performing a read on boards using DDR3. This optimizes both active and standby power consumption. This bit is not set on EVM SK and EVM 1.5 and later boards. Setting the same. This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
| * ARM: OMAP3: Rename OMAP3_PUBLIC_SRAM_* to NON_SECURE_SRAM_*Enric Balletbò i Serra2014-01-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Other TI processors like am33xx, omap4 and omap5 have called these variables as NON_SECURE_SRAM_*, shouldn't be a big problem rename these variables to be coherent. One reason more to rename these variables is to have the possibility of any OMAP3 board to use the ti_armv7_common.h include as the NON_SECURE_SRAM_END is used to define the CONFIG_SYS_INIT_SP_ADDR variable. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
| * ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALLJassi Brar2014-01-24-8/+0
| | | | | | | | | | | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALLJassi Brar2014-01-24-227/+0
| | | | | | | | | | | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | spl: common: Support for USB MSD FAT image loadingDan Murphy2014-01-24-3/+11
| | | | | | | | | | | | | | | | Add SPL support to be able to detect a USB Mass Storage device connected to a USB host. Once a USB Mass storage device is detected the SPL will load the u-boot.img from a FAT partition to target address. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* | ARM: merge commonly-defined PLATFORM_RELFLAGSMasahiro Yamada2014-01-24-82/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8 had the same option: $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) This commit moves it into arch/arm/config.mk. If the compiler does not support the option, it is ignored by $(call cc-option,...). So this commit gives no harm to ARMv8. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | lib: time: add weak timer_init() functionDarwin Rambo2014-01-24-10/+0
| | | | | | | | | | | | | | | | | | | | If timer_init() is made a weak stub function, then it allows us to remove several empty timer_init functions for those boards that already have a timer initialized when u-boot starts. Architectures that use the timer framework may also remove the need for timer.c. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
* | ARM: bcm2835: fix mailbox timeoutStephen Warren2014-01-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | My original intention was to have a 100ms timeout. However, the timer operations used return values in ms not us, so we ended up with a 100s timeout instead. Fixing this exposes that some operations need longer to operate than 100ms, so bump the timeout up to a whole second. Reported-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | ARM: rpi_b: power on SDHCI and USB HW modulesStephen Warren2014-01-20-0/+48
| | | | | | | | | | | | | | | | | | | | Send RPC commands to the VideoCore to turn on the SDHCI and USB modules. For SDHCI this isn't needed in practice, since the firmware already turned on the power in order to load U-Boot. However, it's best to be explicit. For USB, this is necessary, since the module isn't powered otherwise. This will allow the kernel USB driver to work. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-01-20-65/+0
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| * | mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam2014-01-17-65/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-16-2/+21
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| * | arm: rmobile: Add SH QSPI base register addressNobuhiro Iwamatsu2014-01-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This adds base register address of SH QSPI. Currently, SH QSPI is used only from R8A7790 and R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-15-2/+19
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| | * mx6: Add initial support for the Hummingboard soloFabio Estevam2014-01-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SolidRun has designed the Hummingboard board based on mx6q/dl/solo. Add the initial support for the mx6 solo variant. More information about this hardware can be found at: http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware (Carrier-One was the previous name of Hummingboard). Based on the work from Jon Nettleton <jon.nettleton@gmail.com>. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()Fabio Estevam2014-01-15-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-14-6/+13
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