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* arm: spear: Move to common SPL infrastructureStefan Roese2015-08-28-266/+73
| | | | | | | | | | | | | The SPL implementation for SPEAr600 is older than the common SPL infrastructure. This patch now moves the SPEAr600 SPL over to the common SPL code. Tested on the only SPEAr board that currently uses SPL in mainline U-Boot, the x600. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* ARM: k2l: Fix device speedsLokesh Vutla2015-08-28-2/+2
| | | | | | | | | | | ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Build MLO by defaultLokesh Vutla2015-08-28-0/+4
| | | | | | | | | | | MLO(NAND/MMC boot image), is used for all the ks2 platforms. Enabling it in config.mk so that these images will be automatically built upon calling make. u-boot-spi.gph is already the build target, so not including here. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Rename u-boot-nand.gph to MLOLokesh Vutla2015-08-28-2/+4
| | | | | | | | | | | | | | NAND boot mode, ROM expects an image with a gp header in the beginning and an 8bytes filled with zeros at the end. The same is true for SD boot on K2G platforms but the file name should be MLO. Renaming u-boot-nand.gph to MLO, so that same image can be used for NAND and SD boots. And also not including all the u-boot only images under CONFIG_SPL_BUILD. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: move the custom build rules out to keystone specific makefileNishanth Menon2015-08-28-0/+22
| | | | | | | | | | | | | | | Keystone has build rules introduced by commit ef509b9063fb7 ("k2hk: add support for k2hk SOC and EVM") and commit 0e7f2dbac6ead ("keystone: add support for NAND gpheader image"). These are not reused by other platforms for the build, hence there is no clear benefit is maintaining them in the generic makefile as a build target. move these to the keystone specific make option Original idea of using config.mk by Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-28-0/+16
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-28-0/+11
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-08-26-0/+2
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| * mtd: nand: mxs support oobsize bigger than 512Peng Fan2015-08-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ecc chunk data size is 512 and oobsize is bigger than 512, there is a chance that block_mark_bit_offset conflicts with bch ecc area. The following graph is modified from kernel gpmi-nand.c driver with each data block 512 bytes. We can see that Block Mark conflicts with ecc area from bch view. We can enlarge the ecc chunk size to avoid this problem to those oobsize which is larger than 512. | P | |<----------------------------------------------------------------->| | | | (Block Mark) | | P' | | | | |<--------------------------------------------------->| D | | O'| | |<--------->| |<->| V V V V V +---+--------------+-+--------------+-+--------------+-+----------+-+---+ | M | data |E| data |E| data |E| data |E| | +---+--------------+-+--------------+-+--------------+-+----------+-+---+ ^ ^ | O | |<---------------->| P : the page size for BCH module. E : The ECC strength. G : the length of Galois Field. N : The chunk count of per page. M : the metasize of per page. C : the ecc chunk size, aka the "data" above. P': the nand chip's page size. O : the nand chip's oob size. O': the free oob. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com>
* | arm: pxa: clean-up include file orderMarcel Ziswiler2015-08-24-3/+3
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | arm: pxa: use common timer functionsAndrew Ruder2015-08-24-69/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves pxa to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) pxa timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locked the processor. Rather than patch the specific pxa issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
* | pxa: Fix boot hang by avoiding vector relocationAndrew Ruder2015-08-24-0/+24
|/ | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") pxa does not boot anymore. Add a specific relocate_vectors macro that skips the vector relocation, as the pxa SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows pxa to boot again. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
* Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-08-23-34/+769
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig Merged these by hand and re-ran savedefconfig on them. Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: socfpga: Fix SD/MMC boot on ArriaV SoCDKMarek Vasut2015-08-23-0/+6
| | | | | | | | | | | | | | Add the missing DT nodes, so that ArriaV SoCDK can boot from SD card. The SD card must be in slot J5 and BSEL must be 0x5. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: dts: Add bank-name property to each GPIO bankMarek Vasut2015-08-23-0/+3
| | | | | | | | | | | | | | | | Add "bank-name" property to each GPIO bank to give it unique name. The approach here is exactly the same as with the "regulator-name" property for regulators. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Make the pinmux table const u8Marek Vasut2015-08-23-6/+4
| | | | | | | | | | | | | | | | | | | | | | Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Switch to filtered QTS filesMarek Vasut2015-08-23-30/+8
| | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Add qts-filter.sh scriptMarek Vasut2015-08-23-0/+205
| | | | | | | | | | | | | | | | | | Add script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Split Altera socfpga into AV and CV SoCDKMarek Vasut2015-08-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Unbind CPU type from board typeMarek Vasut2015-08-23-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Move wrappers into platform directoryMarek Vasut2015-08-23-0/+545
| | | | | | | | | | | | | | | | | | Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Do not enable gmac1 in Cyclone V dtsiMarek Vasut2015-08-23-6/+1
| | | | | | | | | | | | | | | | | | | | | | The GMAC which is enabled is purely board property, so do not enable arbitrary GMAC in DT include files. Same goes for PHY mode, which is again a board property. The CycloneV SoCDK does this correctly, but SoCrates doesn't. This bug never manifested itself though, since all the boards ever used the GMAC1 . This bug manifests itself only on boards that utilise GMAC0. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Make the DT mmc node consistentMarek Vasut2015-08-23-3/+2
| | | | | | | | | | | | | | | | The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node. This makes aliases not very usable, so make everything into mmc0. Moreover, zap the useless mmc alias while at this. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Fix delay in clock managerMarek Vasut2015-08-23-7/+5
| | | | | | | | | | | | | | | | This code claims it needs to wait 7us, yet it uses get_timer() function which operates with millisecond granularity. Use timer_get_us() instead, which operates with microsecond granularity. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Fix delay in freeze controllerMarek Vasut2015-08-23-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: at91: add support for mini-box picosam9g45 boardErik van Luijk2015-08-21-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bootlog: U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21) mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 33024000 Hz, block size 512 reading u-boot.img reading u-boot.img U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000) CPU: AT91SAM9G45 Crystal frequency: 12 MHz CPU clock : 400 MHz Master clock : 133.333 MHz Watchdog enabled DRAM: 256 MiB WARNING: Caches not enabled MMC: mci: 0 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 33333333 Hz, block size 512 reading uboot.env In: serial Out: serial Err: serial Net: macb0 Error: macb0 address not set. Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [add 'picosam9g45_defconfig' to MAINTAINERS] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: at91: pmc: replace the constant with a define in at91_pmc.hErik van Luijk2015-08-21-0/+1
| | | | | | | | | | | | | | | | To enable the clocks on the at91 boards a constant (0x4) is used. This is replaced with a define in at91_pmc.h (1 << 2). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: at91: mpddr: allow multiple DDR controllersErik van Luijk2015-08-21-21/+26
|/ | | | | | | | | The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller. This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [remove 'new blank line at EOF'] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: davinci: remove support for cam_enc_4xxMasahiro Yamada2015-08-20-5/+0
| | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* Merge git://git.denx.de/u-boot-usbTom Rini2015-08-19-0/+6
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| * usb: spear: Add support for both SPEAr600 EHCI controllersStefan Roese2015-08-19-0/+6
| | | | | | | | | | | | | | | | | | | | | | USB EHCI on SPEAr600 has not been tested for a while. The base controller addresses are missing. This patch adds the defines to the header. And adds the missing code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Marek Vasut <marex@denx.de>
* | ARM: dts: Rename memory@0 to memoryMichal Simek2015-08-19-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | zynq-7000.dtsi include skeleton.dtsi which contains memory node with base address and size zero. If you add memory@0 node to the platform DTS in final DTB there are two memory nodes and U-Boot works with the first one (with zeros) which end up in failing in dram_init because size is zero. Platform memory node should rewrite default memory node setup from skeleton.dtsi that's why platfroms needs to also use memory as node name instead of memory@0. Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynqmp: usb: Add usb dwc3 driver support for zynqmpSiva Durga Prasad Paladugu2015-08-19-0/+6
| | | | | | | | | | | | | | | | | | | | Added usb dwc3 driver support for zynqmp this also supports the DFU and LTHOR to download the linux images on to RAM and cen be booted from those linux images. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: drop "optional" from board select in favor of ZC702Masahiro Yamada2015-08-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | One disadvantage of commit a26cd04920dc (arch: Make board selection choices optional) is that Kconfig could create such an insane .config file that no board is selected. Rip off the "optional" again in favor of ZC702 as the default target. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynqmp: Add platform specific arch_get_page_tableMichal Simek2015-08-19-0/+5
| | | | | | | | | | | | | | | | | | Based on the patch: "armv8: caches: Added routine to set non cacheable region" (sha1: dad17fd51027ad02ac8f02deed186d08109d61fd) it is necessary to add platform specific hook. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynqmp: Enable U-Boot run in EL3Michal Simek2015-08-19-0/+8
|/ | | | | | | Enable Secure IOU setup to enable U-Boot to run in EL3 without setting from ATF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-18-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROLMasahiro Yamada2015-08-18-14/+0
| | | | | | | | | | | | | | | | | | | As we discussed a couple of times, negative CONFIG options make our life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ... and here is another one. Now, there are three boards enabling OF_CONTROL on SPL: - socfpga_arria5_defconfig - socfpga_cyclone5_defconfig - socfpga_socrates_defconfig This commit adds CONFIG_SPL_OF_CONTROL for them and deletes CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert the logic. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* lpc32xx: add common USB OHCI defines for all LPC32xx boardsVladimir Zapolskiy2015-08-18-0/+9
| | | | | | | | The change adds a number of macro definitions used by USB OHCI driver, if CONFIG_USB_OHCI_LPC32XX is selected from a board config file. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* usb: lpc32xx: add host USB driverSylvain Lemieux2015-08-18-0/+19
| | | | | | | | | | | | | Incorporate USB driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx USB driver - lpc3250 header file USB registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: move common SLC NAND defines to arch/config.hVladimir Zapolskiy2015-08-18-0/+29
| | | | | | | | | | | | | | | A number of LPC32xx SLC NAND defines is dictated by controller hardware limits and OOB layout is defined by operating system, the definitions are common for all users. Since those macro are used in out of NAND SLC driver code (simple NAND SPL framework), they can not be placed into the driver, therefore move them from board config files to arch/config.h The change also adds OOB layout details specific to small page NAND devices taken from Linux kernel. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* dma: lpc32xx: add DMA driverSylvain Lemieux2015-08-18-0/+78
| | | | | | | | | | | | | Incorporate DMA driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx DMA driver - lpc3250 header file DMA registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-08-18-0/+205
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| * ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspiVignesh R2015-08-17-0/+5
| | | | | | | | | | | | | | | | | | | | | | Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode Also add EDMA3 base address for DRA7XX and AM57XX. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * dma: ti-edma3: Add helper function to support edma3 transferVignesh R2015-08-17-0/+2
| | | | | | | | | | Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: AM43XX: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+36
| | | | | | | | | | | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: OMAP5: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+52
| | | | | | | | | | | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: OMAP5: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+57
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: AM43xx: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+53
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-08-18-7/+5
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