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* Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigsTom Rini2017-03-09-5/+1
| | | | | | | | | | | | | | | | | | | | | | In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* armv8: spl: Call spl_relocate_stack_gd for ARMv8Philipp Tomsich2017-03-01-2/+12
| | | | | | | | | | As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* armv5te: make 'ret lr' produce iinterworking 'bx lr'Albert ARIBAUD2017-03-01-1/+1
| | | | | | | | | | | | | | | | | Current ARM assembler helper for the 'return to caller' pseudo-instruction turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain in its current ARM state even when the routine doing the 'ret' was called from Thumb-1 state, triggering an undefined instruction exception. This causes early run-time failures in all boards compiled using the Thumb-1 instruction set (for instance the Open-RD family). ARMv5TE supports 'bx lr' which properly implements interworking and thus correctly returns to Thumb-1 state from ARM state. This change makes 'ret lr' turn into 'bx lr' for ARMv5TE. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: mach-omap2: Flush cache after FIT post-processing imageAndrew F. Davis2017-02-27-0/+6
| | | | | | | | | | After we authenticate/decrypt an image we need to flush the caches as they may still contain bits of the encrypted image. This will cause failures if we attempt to jump to this image. Reported-by: Yogesh Siraswar<yogeshs@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: set up charge pump current for MPLL of LD11 SoCMasahiro Yamada2017-02-23-0/+24
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add simple eMMC load APIs instead of ROM APIMasahiro Yamada2017-02-23-58/+195
| | | | | | | | | | | Re-use of routines embedded in the Boot ROM requires a function pointer table for each SoC. This is not nice in terms of the maintainability in a long run. Implement simple eMMC load APIs that are commonly used for LD11, LD20, and hopefully future SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20Masahiro Yamada2017-02-23-1/+25
| | | | | | | | | | | | | For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device would stay in the reset state until its RST_n pin is deasserted by software. Currently, this is cared by an ad-hoc way because the eMMC hardware reset provider is not supported in U-Boot for now. This code should be re-written once the "mmc-pwrseq-emmc" binding is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoCKotaro Hayashi2017-02-23-2/+8
| | | | | | | | | | If the DRAM clock duty does not meet the allowable tolerance, it is marked in an efuse register. If the register is fused, the boot code should compensate for the DRAM clock duty error. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: simplify code, add git-log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove dram_nr_ch from board parametersMasahiro Yamada2017-02-23-26/+18
| | | | | | | This parameter is redundant because we can know the number of channels by checking if dram_ch[2].size is zero. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework spl_boot_device() and related codeMasahiro Yamada2017-02-23-344/+312
| | | | | | | | The current implementation has ugly switch statements here and there, and duplicates similar code. Rework it using table lookups for SoC data and reduce code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move spl_boot_mode() to a separate fileMasahiro Yamada2017-02-23-24/+35
| | | | | | | | The spl_boot_mode() is unrelated to the other code in this file. Besides, this function is only called from common/spl/spl_mmc.c, so it is reasonable to guard with CONFIG_SPL_MMC_SUPPORT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move MMC code to a separate fileMasahiro Yamada2017-02-23-38/+47
| | | | | | | | | | Currently, arch/arm/mach-uniphier/boot-mode/boot-mode.c is messed up with unrelated code; there is no reason why the "mmcsetn" command must be placed in this file. Split out the MMC code into arch/arm/mach-uniphier/mmc-first-dev.c. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: drop u-boot, dm-pre-reloc from system-bus pinctrl nodeMasahiro Yamada2017-02-23-8/+0
| | | | | | | | Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), SPL does not need pin-mux settings for the System Bus. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove DRAM base address from board parametersMasahiro Yamada2017-02-23-57/+36
| | | | | | | | | The base address of each DRAM channel can be calculated from other parameters, so does not need hard-coding. What we need is the size of each DRAM channel and DRAM_SPARSE flag to decide the start address of DRAM channel 1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: print Support Card info very lateMasahiro Yamada2017-02-23-7/+4
| | | | | | | | | | | Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), the System Bus is initialized by board_init(). The show_board_info() is called from board_init_f() by default, so the revision register of the Micro Support Card may not be accessed at this point. Show its revision after the System Bus is initialized. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: skip memreserve of unused DRAM bank of LD20Masahiro Yamada2017-02-23-0/+3
| | | | | | | | Now the "for" loop here iterates on the detected memory banks. It must skip unused DRAM banks. Fixes: c995f3a3c526 ("ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoC") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: correct spelling of "invalid"Masahiro Yamada2017-02-23-3/+3
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: skip MEMCONF ch2 parsing if CH2_DISABLE bit is setMasahiro Yamada2017-02-23-1/+1
| | | | | | | If SG_MEMCONF_CH2_DISABLE bit is set, the DRAM channel 2 is unused. The register settings for the ch2 should be ignored. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: revive accidentally removed dcache_disable()Masahiro Yamada2017-02-23-0/+4
| | | | | | | | | Commit a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") accidentally dropped dcache_disable() call. Since then, the SPL of LD11 and LD20 failed to load U-Boot proper. Fixes: a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: DRA7xx: Fix memory allocation overflowAndrew F. Davis2017-02-17-1/+1
| | | | | | | | | | When using early malloc the allocated memory can overflow into the SRAM scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more dynamic allocation at the expense of a slightly smaller maximum image size. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* SPL: Move SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to KconfigDalon Westergreen2017-02-17-0/+1
| | | | | | | | | | | Added SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION and SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to Kconfig. Due to SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION being moved to Kconfig the board defconfigs for db-88f6820-gp_defconfig kc1_defconfig and sniper_defconfig need to be updated. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
* SPL: add support to boot from a partition typeDalon Westergreen2017-02-17-0/+6
| | | | | | | | | | | | | the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Assigned a partition number of -1 will cause a search for a partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE and use it to find the u-boot image Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
* arm: omap5: Fix generation of reserved-memory DT nodeAndrew F. Davis2017-02-17-1/+6
| | | | | | | | | When the node 'reserved-memory' is not defined in the DT we fail to add needed properties. We also fail to move 'offs' to point to the new node. Fix these here. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* flash: complete CONFIG_SYS_NO_FLASH move with renamingMasahiro Yamada2017-02-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is not completed. Finish this work by the tool. During this move, let's rename it to CONFIG_MTD_NOR_FLASH. Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH" than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will make the code more readable. Besides, negative meaning symbols do not fit in obj-$(CONFIG_...) style Makefiles. This commit was created as follows: [1] Edit "default n" to "default y" in the config entry in common/Kconfig. [2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH" [3] Rename the instances in defconfigs by the following: find . -path './configs/*_defconfig' | xargs sed -i \ -e '/CONFIG_SYS_NO_FLASH=y/d' \ -e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/' [4] Change the conditionals by the following: find . -name '*.[ch]' | xargs sed -i \ -e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \ -e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \ -e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \ -e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/' [5] Modify the following manually - Rename the rest of instances - Remove the description from README - Create the new Kconfig entry in drivers/mtd/Kconfig - Remove the old Kconfig entry from common/Kconfig - Remove the garbage comments from include/configs/*.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-02-11-65/+65
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| * rockchip: rename miniarm to tinker boardEddie Cai2017-02-09-10/+10
| | | | | | | | | | | | | | | | Miniarm is the internal project code. Now it is officially named Tinker board. So rename it. Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: rk3288: correct sdram setting for miniarmJacob Chen2017-02-09-8/+8
| | | | | | | | | | | | | | | | | | | | | | miniarm board use lpddr3 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Added 'rockchip:' prefix to subject: Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I84c3679dab2dbd8d01c1ebfd22220946d07c03cd
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2017-02-09-2/+2
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| * | net: phy: dp83867: Add support for MAC impedance configurationMugunthan V N2017-02-07-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for programmable MAC impedance configuration and fix typo in DT impedance parameters names. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2017-02-09-8/+142
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| * | | arm: dts: trats: add the pmic node for using DMJaehoon Chung2017-02-09-8/+142
| | |/ | |/| | | | | | | | | | | | | | | | | | | To use driver-model adds the pmic node for max8997. This is used as kernel device-tree in Linux. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2017-02-08-0/+9
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| * | arm: socfpga: set the mpuclk divider in the Altera group registerDinh Nguyen2017-02-08-0/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll. Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-02-08-2/+2
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| * | dm: core: Replace of_offset with accessorSimon Glass2017-02-08-2/+2
| |/ | | | | | | | | | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | cmd: move CONFIG_CMD_UNZIP and CONFIG_CMD_ZIP to KconfigMasahiro Yamada2017-02-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_CMD_ZIP is not defined by any board. I am moving CONFIG_CMD_UNZIP to defconfig files except UniPhier SoC family. I am the maintainer of UniPhier platform, so I know "select CMD_UNZIP" is better for this platform. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* | arm64: fix comment in relocate_64.SMasahiro Yamada2017-02-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two typos in the comment "invalide i-cache is enabled". We can fix it by invalide -> invalidate is -> if Or, if we want to match the comment to the code, we can say "skip invalidating i-cache if disabled". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: dts: k2*: Rename the k2* files to keystone-k2* filesLokesh Vutla2017-02-08-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported in [1], rename the k2* dts files to keystone-* files this will force consistency throughout. Script for the same (and hand modified for Makefile and config files): for i in arch/arm/dts/k2* do b=`basename $i`; git mv $i arch/arm/dts/keystone-$b; sed -i -e "s/$b/keystone-$b/g" arch/arm/dts/*[si] done This is similar to linux kernel commit 5edafc29829bc ("ARM: dts: k2*: Rename the k2* files to keystone-k2* files") [1] http://marc.info/?l=linux-arm-kernel&m=145637407804754&w=2 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: use store with auto-incrementMasahiro Yamada2017-02-08-2/+1
| | | | | | | | | | | | | | Save one instruction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm64: use xzr to zero-out the bss sectionMasahiro Yamada2017-02-08-2/+1
|/ | | | | | | AArch64 has a zero register (xzr). Use it instead of x2. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-02-03-24/+30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig
| * arch: arm: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-24/+5
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: freescale: ls1012a: Enable secure DDR on LS1012A platformsPrabhakar Kushwaha2017-02-03-0/+3
| | | | | | | | | | | | | | | | | | | | | | PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable workaround for erratum A-008336York Sun2017-01-31-0/+1
| | | | | | | | | | | | | | Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * armv8: ls1046a: added usb nodes in dtsTang Yuantian2017-01-27-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-02-01-30/+3075
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| * | BOARD: MCCMON6: Provide support for iMX6q based mccmon6 boardLukasz Majewski2017-01-30-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides u-boot support for Liebherr (LWN) mccmon6 board. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: dts: imx53-cx9020: fix packetloss on fec_mxcPatrick Bruenn2017-01-30-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmuxing for i.MX53 FEC ethernet copied from <kernel>/arch/arm/boot/dts/imx53-qsb-common.dtsi (at least until v4.9) was bad. It is different from the manual pinmuxing in <u-boot>/board/freescale/mx53loco/mx53loco.c which was used in cx9020 implementation previously before mainlining into u-boot. It seems the bug in imx53-qsb kernel device tree is hidden for so long, because it was never used, by the kernel driver. Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
| * | imx: dts: mx6sxsabreauto: enable i2c2/3Peng Fan2017-01-27-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Enable i2c2/3, add pinctrl settings. Add max7310 for i2c3. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6sx: add dts for mx6sxsabreauto boardPeng Fan2017-01-27-0/+3003
| | | | | | | | | | | | | | | | | | | | | | | | Add dts for mx6sxsabreauto board. dts related files imported fro Linux (commit e5517c2a5a4). Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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