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| * armv8: fsl-layerscape: spl: remove BSS clearing and board_init_rQianyu Gong2016-09-14-5/+0
| | | | | | | | | | | | | | | | | | | | As per the top level U-Boot README "Board Initialisation Flow" section, board_init_f() should return without calling board_init_r() directly. Clearing BSS and calling board_init_r() will be done in crt0_64.S. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone appShaohui Xie2016-09-14-0/+2
| | | | | | | | | | | | | | | | The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latencyMingkai Hu2016-09-14-0/+15
| | | | | | | | | | | | | | | | | | | | | | According to design specification, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, so increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-14-1/+248
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add EPU Finite State MachineHongbo Zhang2016-09-14-0/+165
| | | | | | | | | | | | | | | | The EPU Finite State Machie (FSM) is used in both the last stage of system suspend and the earliest stage of system resume. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add registers definition for system sleepHongbo Zhang2016-09-14-1/+53
| | | | | | | | | | | | | | | | This patch adds definitions of all the regesters necessary for system sleep. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: psci: make v7_flush_dcache_all public for all psci codeHongbo Zhang2016-09-14-3/+5
| | | | | | | | | | | | | | | | | | | | | | The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-14/+0
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+41
| | | | | | | | | | | | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-14-4/+10
| | | | | | | | | | | | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang2016-09-14-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ls1043ardb: PPA: add PPA validation in case of secure bootSumit Garg2016-09-14-0/+39
| | | | | | | | | | | | | | | | | | | | As part of Secure Boot Chain of trust, PPA image must be validated before the image is started. The code for the same has been added. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Update ddr erratum a008336Shengzhou Liu2016-09-14-2/+4
| | | | | | | | | | | | | | | | | | DDR erratum A008336 only applies to DDR controller v5.2.0. DDR controller v5.2.1 already has default 0x43b30002 in EDDRTQCR1 register for optimal performance. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: mvebu: NAND support for DB-88F6820-AMCChris Packham2016-09-24-0/+8
| | | | | | | | | | | | | | Enable the NAND interface on this board. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: add DB-88F6820-AMC boardChris Packham2016-09-24-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is a plug in card for Marvell's switch system development kits. Form-factor aside it is similar to the DB-88F6820-GP with the following differences. - TCLK is 200MHz - SPI1 is used - No SATA - No MMC - NAND flash Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: create generic 88F6820 config optionChris Packham2016-09-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | 88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards using the 88F6820 can be added. Stefan: Change 88F6820 for clearfog as well. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | treewide: replace #include <asm-generic/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>. Replace all include directives for <asm-generic/errno.h> with <linux/errno.h>. <asm-generic/...> is supposed to be included from <asm/...> when arch-headers fall back into generic implementation. Generally, they should not be directly included from .c files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Add drivers/usb/host/xhci-rockchip.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-23-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
* | treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-43/+43
| | | | | | | | | | | | | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* | arch, board: squash lines for immediate returnMasahiro Yamada2016-09-23-18/+5
| | | | | | | | | | | | | | | | Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Angelo Dureghello <angelo@sysam.it>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-09-22-8/+454
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| * | rk3399: add a empty "sys_proto.h" header fileKever Yang2016-09-22-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | driver/usb/dwc3/gadget.c need a "sys_proto.h" header file, add a empty one to make compile success. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: skip lowlevel_init processXu Ziyuan2016-09-22-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | lowlevel_init() is never needed for rk3288, so drop it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | dts: rk3399-evb: add regulator-fixed for usb host vbusKever Yang2016-09-22-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | rk3399 evb using one gpio to enable 5V output for both USB 2.0 host port, let's use fixed regulator for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dts: rk3399: add dwc3_typec node for rk3399MengDongyang2016-09-22-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | rk3399 has two dwc3 controller for type-C port, add the dts node and enable them. Signed-off-by: MengDongyang <daniel.meng@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: select DM_USB for rockchip SoCMengDongyang2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Select DM_USB to compatible with USB DM driver model. Signed-off-by: MengDongyang <daniel.meng@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rk3288: add arch_cpu_init for rk3288Kever Yang2016-09-22-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | We do some SoC level one time setting initialization in arch_cpu_init. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: use dummy byte only enable OF_PLATDATAXu Ziyuan2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a condition to determine the rk3288_sdram_channel size. This patch fixes read sdram_channel property failed from DT on rk3288 boards, which not enable OF_PLATDATA. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * | dts: rk3399: add pinctrl for sdmmcKever Yang2016-09-22-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | This patch add pinctrl for sdcard which may not be initialized before uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: add driver for rk3399Kever Yang2016-09-22-0/+321
| | | | | | | | | | | | | | | | | | | | | This patch add pinctrl driver for rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rk3399: syscon: add support for pmugrfKever Yang2016-09-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | pmugrf is a module like grf which contain some of the iomux registers and other registers. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-09-22-203/+374
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| * | | ARM: dts: uniphier: sync clock/reset controller nodes with LinuxMasahiro Yamada2016-09-23-181/+301
| | | | | | | | | | | | | | | | | | | | | | | | Sync device trees with Linux for easier DT life. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: uniphier: add PLL init code for LD11 SoCMasahiro Yamada2016-09-23-7/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: uniphier: move CONFIG_SPL_* to defconfig or selectMasahiro Yamada2016-09-23-15/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As I repeated in the ML, I am unhappy with config entries with bare defaults. Kick them out of arch/arm/mach-uniphier/Kconfig. Currently, CONFIG_SPL_SERIAL_SUPPORT is not user-configurable (build fails without it), but it should be fixed later anyway, so I am moving CONFIG_SPL_SERIAL_SUPPORT to defconfigs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM64: zynqmp: Fix USB ulpi phy sequenceMichal Simek2016-09-22-4/+0
| | | | | | | | | | | | | | | | | | | | | It should be enough to call low(5us)->high pulse for all cases to provide proper reset. There is no need to call high->low->high. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Add support for USB ulpi phy reset via mode pinsMichal Simek2016-09-22-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mode pins can be used as output for reset. Xilinx boards are using this feature as additional way how to reset USB phys and also others chips on the boards. Mode1 is used on all these boards for this feature. Let SPL toggle reset on this pin by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Add support for DFU from SPLMichal Simek2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL needs to have bigger stack size because of USB. Simple malloc needs to be disabled because dfu code requires different allocation functions. There is no space in OCM that's why random place in DDR is used. BOOTD must be disabled because it is causing compilation error. All variables are disabled and used only variables valid for DFU because they are simple huge. Including automatic variables added by CONFIG_ENV_VARS_UBOOT_CONFIG. Hardcode addresses for u-boot, atf, kernel and dtb just for SPL DFU code. Enable SPL DFU for zcu100. Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM: Add new BOOT_DEVICE_DFU boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | This enum is needed when SPL_DFU is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Add USB boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | Add USB boot mode. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-09-22-0/+57
|/ / | | | | | | | | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-09-18-1025/+1148
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| * | ARM: uniphier: update DRAM init code for LD20 SoCMasahiro Yamada2016-09-19-62/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import the latest version from the Diag software. - Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add PLL init code for LD20 SoCMasahiro Yamada2016-09-19-5/+234
| | | | | | | | | | | | | | | | | | | | | | | | Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: collect clock/PLL init code into a single directoryMasahiro Yamada2016-09-19-24/+18
| | | | | | | | | | | | | | | | | | | | | | | | Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move PLL init code to U-Boot proper where possibleMasahiro Yamada2016-09-19-495/+365
| | | | | | | | | | | | | | | | | | | | | | | | The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PERMasahiro Yamada2016-09-18-1/+1
| | | | | | | | | | | | | | | | | | Basically, this should not be configured by users. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-08 09:02:19 +0000