summaryrefslogtreecommitdiff
path: root/arch/arm
Commit message (Collapse)AuthorAgeLines
...
| * | ARM: SPL: Start hooking in the current SPI SPL supportTom Rini2012-09-27-0/+8
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: SPL: Clean up spl.c / spl_nand.c slightlyTom Rini2012-09-27-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove includes we don't need - Switch some printf statements to puts - Convert some printf statements to debug, introduce new puts statements - In most cases saying just "No mkimage signature, assuming u-boot.bin" or similar is sufficient. This also means the non-DEBUG case doesn't need printf, in the core of SPL. - The other case here is that PLAIN_VERSION provided what we wanted already, so just use it. Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: SPL: Make spl_mmc.c more genericTom Rini2012-09-27-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | Move the default omap/related-centric board_mmc_init to arch/arm/cpu/armv7/omap-common/boot-common.c and move the type defines to <asm/spl.h>. Also use mmc->read_bl_len rather than MMCSD_SECTOR_SIZE Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: SPL: Add <asm/spl.h> and <asm/arch/spl.h>Tom Rini2012-09-27-76/+203
| | | | | | | | | | | | | | | | | | | | | Move the SPL prototypes from <asm/omap_common.h> into <asm/spl.h> and add <asm/arch/spl.h> for arch specific portions of CONFIG_SPL_FRAMEWORK. Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: SPL: Only call mem_malloc_init if configuredTom Rini2012-09-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | We can only attempt to setup a malloc pool if CONFIG_SYS_SPL_MALLOC_START is defined, and not all boards require it. Make the call depend on the define. Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: SPL: Remove NAND_MODE_HW_ECC from spl_nand.cTom Rini2012-09-27-14/+3
| | | | | | | | | | | | | | | | | | | | | This detection code doesn't (and can't) do anything currently, so remove. Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: SPL: Rename omap_boot_mode to spl_boot_mode()Tom Rini2012-09-27-5/+5
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: SPL: Rename omap_boot_device to spl_boot_deviceTom Rini2012-09-27-8/+8
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | omap-common: SPL: Fix whitespace in omap-common/u-boot-spl.lds.Pavel Machek2012-09-27-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
| * | omap-common: Fix typo in save_boot_params() in lowlevel_init.STom Rini2012-09-27-1/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | omap-common: SPL: Add CONFIG_SPL_DISPLAY_PRINT / spl_display_print()Tom Rini2012-09-27-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Only omap4/5 currently have a meaningful set of display text and overo had been adding a function to display nothing. Change how this works to be opt-in and only turned on for omap4/5 now. Signed-off-by: Tom Rini <trini@ti.com>
| * | spl_mmc: Make FAT checks / calls guarded with CONFIG_SPL_FAT_SUPPORTTom Rini2012-09-27-0/+4
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: arm1176: Define arch_cpu_init() at the SoC levelStephen Warren2012-09-25-8/+25
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Commit 86c6326 "ARM: arm1176: enable instruction cache in arch_cpu_init()" defined arch_cpu_init() in a file that is shared across all arm1176 SoCs. tnetv107x already implemented this function, which caused linking to break. Move the new conflicting arch_cpu_init() into arm1176/bcm2835/init.c so that it doesn't conflict; grep indicates this function is usually defined at the SoC-level, not the CPU-level, at least for ARM. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Marek Vasut <marex@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-269/+448
| |\
| * | ARM: Remove apollon boardMarek Vasut2012-09-18-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is the only board that still sticks to OneNAND IPL. Remove this board, since we have SPL around for a while and OneNAND is well supported in the SPL framework. The board can be revived if necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Tom Rini <trini@ti.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2012-09-17-1/+2
| |\ \
| | * | omap4 i2c: add support for i2c bus 4Koen Kooi2012-09-06-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
| * | | mmc: s5p_sdhci: fixed wrong function argumentJaehoon Chung2012-09-05-4/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Useless code is removed, and get buswidth value. buswidth value will be used to choice the 4bit or 8bit. (Now used 4bit mode in sdhci.c by default) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-09-02-0/+159
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: MUSB driver: Timeout is never detected as the while loop does not end usb: fix ulpi_set_vbus prototype pxa25x: Add UDC registers definitions USB: Fix strict aliasing in ohci-hcd usb: Optimize USB storage read/write ehci: Optimize qTD allocations usb_stor_BBB_transport: Do not delay when not required usb_storage: Remove EHCI constraints usb_storage: Restore non-EHCI support ehci-hcd: Boost transfer speed ehci: cosmetic: Define used constants ehci: Fail for multi-transaction interrupt transfers arm:trats: Enable g_dnl composite USB gadget with embedded DFU function on TRATS arm:trats: Support for USB UDC driver at TRATS board. dfu:cmd: Support for DFU u-boot command dfu: MMC specific routines for DFU operation dfu: DFU backend implementation dfu:usb: DFU USB function (f_dfu) support for g_dnl composite gadget dfu:usb: Support for g_dnl composite download gadget. ehci: cosmetic: Define the number of qt_buffers Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | pxa25x: Add UDC registers definitionsŁukasz Dałek2012-09-01-0/+159
| | | | | | | | | | | | | | | | Signed-off-by: Łukasz Dałek <luk0104@gmail.com>
* | | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-29-0/+11
|\ \ \ \ | |_|_|/ |/| | |
| * | | i.MX: shut down video before launch of O/SEric Nelson2012-09-24-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | | mx51evk: Add CONFIG_REVISION_TAGBenoît Thébaudeau2012-09-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-21-190/+218
|\ \ \ \ | |/ / /
| * | | MX6: drop binary constants from iomux headerStefano Babic2012-09-17-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | MX: set a common place to share code for Freescale i.MXStefano Babic2012-09-10-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up now only MX5 and MX6 can share code, because they have a common source directory in cpu/armv7. Other not armv7 i.MX can profit of the same shared code. Move these files into a directory accessible for all, similar to plat-mxc in linux. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | mx31: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-10/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX31 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Helmut Raiger <helmut.raiger@hale.at>
| * | | Fix mx31_decode_pllBenoît Thébaudeau2012-09-06-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | mx35 timer: Switch to 32-kHz sourceBenoît Thébaudeau2012-09-06-17/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the mx35 timer driver to the 32-kHz clock source to avoid calling mxc_get_clock() again and again, and to be consistent with the timer drivers of other i.MX SoCs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mx35: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX35 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mx25: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX25 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Matthias Weisser <weisserm@arcor.de>
| * | | mx35: Fix clock dividersBenoît Thébaudeau2012-09-06-59/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | mx35: Add definitions for clock gate valuesBenoît Thébaudeau2012-09-06-0/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | mx35: Fix decode_pllBenoît Thébaudeau2012-09-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | MX28: Fixup the ad-hoc use of DIGCTL_MICROSECONDSMarek Vasut2012-09-04-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use proper struct-based access for this register in the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | | Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren2012-09-10-43/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | | | tegra20: usb: rework set_host_modeLucas Stach2012-09-10-16/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows for two things: - VBus GPIO may be used on other ports than the OTG one - VBus GPIO may be low active if specified by DT Signed-off-by: Lucas Stach <dev@lynxeye.de> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <TWarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: nand: Add Tegra NAND driverJim Lin2012-09-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: fdt: Add NAND controller binding and definitionsSimon Glass2012-09-07-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a NAND controller along with a bindings file for review. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: Add NAND support to funcmuxSimon Glass2012-09-07-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add selection of NAND flash pins to the funcmux. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | Merge remote-tracking branch 'u-boot-ti/master' into mAlbert ARIBAUD2012-09-05-21/+15
|\ \ \ \
| * | | | am33xx: Remove redundant timer configTom Rini2012-09-04-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that has been configuring and enabling the timer, so remove our code that does the same thing by different methods. Tested on EVM GP, SK-EVM and Beaglebone. Signed-off-by: Tom Rini <trini@ti.com>
| * | | | OMAP3: video: add macros to set display parametersStefano Babic2012-09-04-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common macros to set the registers for horizontal and vertical timing. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | | video: drop duplicate set of DISPC_CONFIG registerStefano Babic2012-09-04-1/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | | OMAP3: add definition of CTRL_WKUP_CTRL registerArnout Vandecappelle (Essensium/Mind)2012-09-04-0/+5
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM/DM37x SoCs add the CTRL_WKUP_CTRL register. It contains the GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads of gpio_126, gpio_127 and gpio_129. Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Tom Rini <trini@ti.com>
* | | | arm: Adds board_postclk_init to the init_sequence.Markus Hubig2012-09-04-0/+3
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | The board_postclk_init() function can be used to perform operations that requires a working timer early within the U-Boot init_sequence. Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | kw_spi: fix clock prescaler computationValentin Longchamp2012-09-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The computation was not correct with low clock values: setting a 1MHz clock would result in an overlap that would then configure a 25Mhz clock. This patch implements a correct computation method according to the kirkwood functionnal spec. table 600 (Serial Memory Interface Configuration Register). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* | | edminiv2: orion5x: fix GPIO inits and valuesAlbert ARIBAUD2012-09-03-0/+2
|/ / | | | | | | | | | | | | | | | | Orion5x did not actually write GPIO output values or input polarities, and ED Mini V2 had bad or missing values for GPIO settings. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
* | atmel: at91sam9x5: fix name error for spiBo Shen2012-09-01-2/+2
| | | | | | | | | | | | | | Fix the name error Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mxc: Define architecture identifierBenoît Thébaudeau2012-09-01-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com>
generated by cgit v1.1 at 2024-11-11 22:18:33 +0000