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* ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.cMasahiro Yamada2016-02-14-1/+8
| | | | | | | | The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram to build these commands. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused header mio-regs.hMasahiro Yamada2016-02-14-20/+0
| | | | | | | | | This header is no longer used. This is the last file in arch/arm/mach-uniphier/include/mach/. At last, I've succeeded in eliminating the mach directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop unneeded EHCI pin mux settingsMasahiro Yamada2016-02-14-25/+0
| | | | | | | These pin mux settings are cared by the pinctrl drivers. Remove the ad-hoc code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: switch over to generic EHCI driverMasahiro Yamada2016-02-14-8/+8
| | | | | | | | | | | | The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does nothing special but set the base address and handle reset/clock. Since commit 4feefdcfe916 ("usb: add clock support for generic EHCI"), the generic one (drivers/usb/host/ehci-generic.c) can do those, too. We no longer need to stick to the dedicated driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add clocks properties to EHCI nodesMasahiro Yamada2016-02-14-0/+12
| | | | | | This allows the EHCI driver to get clocks from device tree. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add device nodes for MIO control blockMasahiro Yamada2016-02-14-0/+44
| | | | | | | This block provides clock and reset control for MIO (Media I/O) hardware blocks such as USB2.0, SD card, eMMC, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add device nodes for Peripheral control blockMasahiro Yamada2016-02-14-0/+36
| | | | | | | This block provides clock and reset control for peripherals such as UART, I2C, IC card, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add device nodes for System Control blocksMasahiro Yamada2016-02-14-0/+36
| | | | | | These are mainly used for controlling clocks and resets. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add reference clock nodesMasahiro Yamada2016-02-14-0/+33
| | | | | | | | | | Add master clock nodes generated by crystal oscillators. PH1-sLD3, PH1-LD4: 24.576 MHz PH1-Pro4, ProXstream2: 25.000 MHz PH1-Pro5: 20.000 MHz Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* clk: uniphier: add Media I/O clock driver for UniPhier SoCsMasahiro Yamada2016-02-14-0/+1
| | | | | | | This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoCMasahiro Yamada2016-02-14-2/+22
| | | | | | | | | | | | | | | | | | The USB boot code is too fat and complicated to be included in SPL (at least for now). So, it was implemented as a separate project (what we call USB-loader). The expected boot sequence is as follows: Boot ROM -> USB-loader -> SPL -> U-Boot proper The USB-loader loads the SPL and U-Boot proper from a USB memory onto the locked L2 cache. Then, SPL needs to copy the U-Boot proper to DRAM, so this mode looks like a NOR boot from the view of SPL. However, we want to distinguish between (genuine) NOR boot and USB boot in some places. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add missing static qualifierMasahiro Yamada2016-02-14-1/+1
| | | | | | This function is for local use in the file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: create early page table at run-timeMasahiro Yamada2016-02-14-38/+94
| | | | | | | | | | | | | | | | | | UniPhier SoCs are not equipped with dedicated on-chip SRAM. Instead, locked outer cache is used as RAM area during the early boot stage where DRAM is not ready yet. This effectively means MMU must be always enabled while we are in SPL. Currently, the SPL image for UniPhier SoCs contains the page table statically defined at compile time. It has been a burden because the 16KB page table occupies a quarter memory footprint of the 64KB SPL image. Finally, there is no more room to implement new features in SPL. Setting aside the NOR boot mode, this issue can be solved by creating the page table onto RAM at run time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: change stack pointer address for SPLMasahiro Yamada2016-02-14-4/+1
| | | | | | | | | | | | | | | | | No special reason for the current stack address 0x0ff08000. Change it to 0x00100000 to simplify the init_page_table. There are two types of SoCs in terms of the load address of SPL. [1] PH1-sLD3, PH1-LD4, PH1-sLD8 SPL is loaded at 0x00040000-0x0004ffff [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b SPL is loaded at 0x00100000-0x0010ffff The new stack area (0x000f8000-0x00100000) should be safe for all the cases. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* spl: define BOOT_DEVICE_USBMasahiro Yamada2016-02-14-0/+1
| | | | | | This enum is referenced from common/spl/spl.c. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boardsMasahiro Yamada2016-02-14-27/+53
| | | | | | | Some of PH1-Pro4 boards are equipped with larger amount of DRAM than the reference board. Add UMC settings to support them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-02-11-0/+1
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| * video: tegra: Enable the 'lcd' env variable work-aroundSimon Glass2016-02-11-0/+1
| | | | | | | | | | | | | | Enable this option on all tegra boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* | ARM: dts: k2g: Add keystone net dts filesMugunthan V N2016-02-08-0/+176
| | | | | | | | | | | | | | | | Add keystone net DT support for k2g evm. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | OMAP3_LOGIC: Setup defconfig to enable SPL and NAND bootingAdam Ford2016-02-08-0/+1
| | | | | | | | | | | | | | | | | | | | The defconfig patch will enable the the SPL and NAND settings. The update to Kconfig will allow the SPL to configured in and built. Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | serial: serial_stm32: move clock config from driver to boardVikas Manocha2016-02-08-0/+62
| | | | | | | | | | | | | | | | This patch removes the uart clock enable from serial driver & move it in the board code. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Use correct spelling of "U-Boot"Bin Meng2016-02-06-20/+20
|/ | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* imx: mx6: implement mmc_get_env_devPeng Fan2016-02-04-0/+32
| | | | | | | | | | Implement mmc_get_env_dev, devno can be got from smbr1 of SRC. Introduce a weak function board_mmc_get_env_dev, different boards can implement it according to different sdhc controllers that used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7dsabresd: move mmc_get_env_devno to soc codePeng Fan2016-02-04-0/+21
| | | | | | | | | | | Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to match the one in common/env_mmc.c. Introduce a weak function board_mmc_get_env_dev. Different boards can implement this according to sdhc controller which is used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* arm: pcm052: Add device tree file'sBhuvanchandra DV2016-02-02-1/+24
| | | | | | | | | - Add device tree files for Phytec phyCORE-Vybrid Board. - Enable lpuart support for Phytec phyCORE-Vybrid Board. - Use UART1 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: vf610-twr: Add device tree file'sBhuvanchandra DV2016-02-02-1/+24
| | | | | | | | | - Add device tree files for NXP/Freescale VF610 Tower Board. - Enable lpuart support on NXP/Freescale VF610 Tower Board. - Use UART1 as stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: colibri-vf: Enable serial supportBhuvanchandra DV2016-02-02-0/+10
| | | | | | | | - Enable lpuart support on Toradex Colibri VF50/VF61 - Use UART0 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: vybrid: Update the license stringBhuvanchandra DV2016-02-02-20/+0
| | | | | | | | Since SPDX license is already there, drop the full one. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: vybrid: Enable lpuart supportBhuvanchandra DV2016-02-02-0/+43
| | | | | | | | Add device tree node's for lpuart on Vybrid platform Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculationYe Li2016-02-02-4/+0
| | | | | | | | | | The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6sx: Fix issue in LCDIF clock enablementYe Li2016-02-02-2/+2
| | | | | | | | Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always enter the -EINVAL return. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO boardYe Li2016-02-02-0/+6
| | | | | | | Initial version for mx6sx SABREAUTO board support with features: PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander. Signed-off-by: Ye Li <ye.li@nxp.com>
* mx6: soc: Add ENET2 mac address supportYe Li2016-02-02-29/+26
| | | | | | | The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading MAC address from fuse for ENET2. Signed-off-by: Ye Li <ye.li@nxp.com>
* arm: imx6: Add DDR3 calibration code for MX6 Q/D/DLMarek Vasut2016-02-02-0/+564
| | | | | | | | | Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code fine-tunes the behavior of the MMDC controller in order to improve the signal integrity and memory stability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-02-14/+221
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| * board: atmel: sama5d2_xplained: add SPL supportWenyou Yang2016-02-02-0/+34
| | | | | | | | | | | | | | | | The sama5d2 Xplained SPL supports the boot medias: spi flash and SD Card. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: mpddrc: use IP version to check configurationWenyou Yang2016-02-02-7/+11
| | | | | | | | | | | | | | | | To remove the unnecessary #ifdef-endif, use the mpddrc IP version to check whether or not the interleaved decoding type is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initializationWenyou Yang2016-02-02-8/+167
| | | | | | | | | | | | | | | | | | | | | | | | The DDR3-SDRAM initialization sequence is implemented in accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section described in the SAMA5D2 datasheet. Add registers and definitions of mpddrc controller, which is used to support DDR3 devices. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: mpddrc: add struct atmel_mpddrc_configWenyou Yang2016-02-02-2/+12
| | | | | | | | | | | | | | | | | | | | Add struct atmel_mpddrc_config to accommodate the mpddrc register configurations, not using the mpddrc register map structure, struct atmel_mpddrc, in order to increase readability and reduce run-time memory use. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-02-0/+71
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| * | arm8: ls2080: Move the core errata defines out of board specific fileAshish kumar2016-02-01-0/+2
| | | | | | | | | | | | | | | | | | | | | Valid for core A57 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Implement workaround for core errata 829520, 833471Ashish kumar2016-02-01-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 829520: Code bounded by indirect conditional branch might corrupt instruction stream. Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor. 833471: VMSR FPSCR functional failure or deadlock. Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043aqds: fix DSPI/QSPI node in dts fileQianyu Gong2016-02-01-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the lost dts info when merging patches. Fix DSPI node for 'commit e0579a5852b3 ("armv8/ls1043aqds: add DSPI support")' and QSPI node for 'commit 166ef1e90ce4 ("armv8/ls1043aqds: add QSPI support in SD boot")'. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | arm: config: enforce -fno-pic for gccPeng Fan2016-01-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Android's tool chain enable the -mandroid at default. This option will enable the -fpic, which cause uboot compilation failure: " LD u-boot u-boot contains unexpected relocations: R_ARM_ABS32 R_ARM_RELATIVE " In my testcase, arm-linux-androideabi-gcc-4.9 internally enables '-fpic', so when compiling code, there will be relocation entries using type R_ARM_GOT_BREL and .got section. When linking all the built-in.o using ld, there will be R_ARM_ABS32 relocation entry and .got section in the final u-boot elf image. This can not be handled by u-boot, since u-boot only expects R_ARM_RELATIVE relocation entry. arm-poky-linux-gnueabi-gcc-4.9 default does not enable '-fpic', so there is not .got section and R_ARM_GOT_BREL in built-in.o. And in the final u-boot elf image, all relocation entries are R_ARM_RELATIVE. we can pass '-fno-pic' to xxx-gcc to disable pic. whether the toolchain internally enables or disables pic, '-fno-pic' can work well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't ↵Wang Dongsheng2016-01-31-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined "DISCARD" will remove ._secure.text relocate, but PSCI framework has already used some absolute address those need to relocate. Use readelf -t -r u-boot show us: .__secure_start addr: 601408e4 .__secure_end addr: 60141460 60141140 00000017 R_ARM_RELATIVE 46 _secure_monitor: 47 #ifdef CONFIG_ARMV7_PSCI 48 ldr r5, =_psci_vectors 60141194 00000017 R_ARM_RELATIVE 6014119c 00000017 R_ARM_RELATIVE 601411a4 00000017 R_ARM_RELATIVE 601411ac 00000017 R_ARM_RELATIVE 64 _psci_table: 66 .word psci_cpu_suspend ... 72 .word psci_migrate 60141344 00000017 R_ARM_RELATIVE 6014145c 00000017 R_ARM_RELATIVE 202 ldr r5, =psci_text_end Solutions: 1. Change absolute address to RelAdr. Based on LDR (immediate, ARM), we only have 4K offset to jump. Now PSCI code size is close to 4K size that is LDR limit jump size, so even if the LDR is based on the current instruction address, there is also have a risk for RelAdr. If we use two jump steps I think we can fix this issue, but looks too hack, so give up this way. 2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined. If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure will in the BASE address that is absolute. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: cache: Implement cache range check for v7Marek Vasut2016-01-31-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* | | arm: Remove S bit from MMU section entryMarek Vasut2016-01-31-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
* | | arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7Marek Vasut2016-01-31-3/+3
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-01-29-1/+22
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| * | ARM: tegra: shut down USB device controller at bootStephen Warren2016-01-28-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When loading U-Boot into RAM over USB protocols using tools such as tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device mode controller is initialized and enumerated by the host PC running the tool. Unfortunately, these tools do not shut down the USB controller before executing the downloaded code, and so the host PC does not "de-enumerate" the USB device. This patch implements optional code to shut down the USB controller when U-Boot boots to avoid leaving a stale USB device present. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-14 23:04:04 +0000