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* | arm: socfpga: reset: Add SDMMC, QSPI and DMA definesMarek Vasut2015-08-08-0/+3
| | | | | | | | | | | | | | Add SDMMC, QSPI and DMA reset defines. These are needed by SPL so that we can boot from SD card and QSPI. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Add function to reset add peripheralsMarek Vasut2015-08-08-0/+14
| | | | | | | | | | | | | | Add socfpga_per_reset_all() function to reset all peripherals but the L4 watchdog. This is needed in the SPL. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Repair bridge reset handlingMarek Vasut2015-08-08-4/+4
| | | | | | | | | | | | | | | | | | | | | | The current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and in case it was (!), the code called hang(). This makes no sense at all. Repair it such that the code instead checks whether the FPGA is programmed, but without any polling involved, and only if it is programmed, it de-asserts the reset. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Replace ad-hoc reset functionsMarek Vasut2015-08-08-64/+13
| | | | | | | | | | | | | | | | Replace all those ad-hoc reset functions, which were all copies of the same invocation of clrbits_le32() anyway, with one single unified function, socfpga_per_reset(), with necessary parameters. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Implement unified function to toggle resetMarek Vasut2015-08-08-23/+37
| | | | | | | | | | | | | | | | Implement function socfpga_per_reset(), which allows asserting or de-asserting reset of each reset manager peripheral in a unified manner. Use this function throughout reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Start reworking the SoCFPGA reset managerMarek Vasut2015-08-08-19/+50
| | | | | | | | | | | | | | | | | | | | Implement macro SOCFPGA_RESET(name), which produces an abstract reset number. Implement macros which allow extracting the reset offset in permodrstN register and which permodrstN register the reset is located in from this abstract reset number. Use these macros throughout the reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: reset: Add missing reset manager regsMarek Vasut2015-08-08-0/+2
| | | | | | | | | | | | | | Define two missing reset manager registers, which are in the SoCFPGA CV datasheet. Signed-off-by: Marek Vasut <marex@denx.de>
* | ddr: altera: Move struct sdram_prot_rule prototypeMarek Vasut2015-08-08-13/+0
| | | | | | | | | | | | | | | | | | | | | | Move the structure prototype from sdram.h header file into sdram.c source file, since it is used only there and for local purpose only. There is no point in having it global. While at this move, fix the data types in the structure from uintNN_t to uNN and fix the coding style a bit. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: Move sdram_config.h to board dirMarek Vasut2015-08-08-100/+0
| | | | | | | | | | | | | | This file is absolutelly positively board specific, so move it into the correct place. Signed-off-by: Marek Vasut <marex@denx.de>
* | driver/ddr/altera: Add DDR driver for Altera's SDRAM controllerDinh Nguyen2015-08-08-12/+399
| | | | | | | | | | | | | | | | This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: dts: socfpga: Add mmc aliasMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | | | | Add alias for the SD/MMC controller, so it can be located by U-Boot OF support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: dts: socfpga: Fix SPI aliasesMarek Vasut2015-08-08-16/+5
|/ | | | | | | | | | | | | The SPI aliases are completely wrong. First, they point to non-existing /spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use ad-hoc string instead of a handle. Furthermore, they are copied multiple times in each board DTS. So fix it such that we move these into socfpga.dtsi and make them use the usual handles. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-239/+1554
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| * exynos: dts: Correct LDO and BUCK namingSimon Glass2015-08-06-63/+63
| | | | | | | | | | | | | | | | At present lower case is used for the regulator names in the device tree. The kernel uses upper case and U-Boot will require this also since it will move to a case-sensitive name check. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Add support for springSimon Glass2015-08-05-0/+595
| | | | | | | | | | | | | | | | | | | | Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: video: Remove non-device-tree codeSimon Glass2015-08-05-2/+0
| | | | | | | | | | | | We always use device tree on exynos, so remove the unused code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Drop the old TPS65090 I2C nodeSimon Glass2015-08-05-16/+0
| | | | | | | | | | | | | | | | While the AP can access the main PMIC on snow, it must coordinate with the EC which also wants access. Drop the old definition, which can in principle generate collision errors. We will use the new arbitration driver instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: exynos: snow: Add a new node for the NXP video bridge driverSimon Glass2015-08-05-20/+16
| | | | | | | | | | | | The driver supports driver model. Add a node for snow, which needs it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: exynos: pit: Add a new node for the parade video bridge driverSimon Glass2015-08-05-5/+123
| | | | | | | | | | | | | | The new driver supports driver model and configuration via device tree. Add a node for pit, which needs this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: exynos: snow: Add memory layout descriptionSimon Glass2015-08-05-0/+53
| | | | | | | | | | | | | | Add a description of the snow memory layout to assist flashing tools which want to be able to deal with any exynos image. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Tidy up CPU frequency displaySimon Glass2015-08-05-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Line up the display with the line below, e.g.: CPU: Exynos5250 @ 1.7 GHz Model: Google Spring DRAM: 2 GiB MMC: EXYNOS DWMMC: 0 Also show the speed as GHz where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Add support for the DisplayPort hotplug detectSimon Glass2015-08-05-0/+11
| | | | | | | | | | | | Allow this function to be selected using the pinmux API. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Enable the debug UART in SPLSimon Glass2015-08-05-0/+5
| | | | | | | | | | | | | | | | As a debugging aid, allow UART3 to be used as a debug UART in SPL. This is a precursor to proper UART support, which requires a substantial refactor. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Support EC tunnel and main TPS65090 regulatorSimon Glass2015-08-05-48/+297
| | | | | | | | | | | | | | | | | | On pit and pi the TPS65090 regulator is connected only to the EC and we must use a tunnel to get to it. The existing U-Boot support relies on a special driver. Add a tunnel definition so that the new device-model TPS65090 driver can be used unmodified. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Add PMIC and regulator definitionsSimon Glass2015-08-05-0/+304
| | | | | | | | | | | | | | | | Snow and smdk5250 use a max77686 PMIC. We have a driver for this, so add the relevant node to the device tree so it can be used. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: dts: Sync up I2C ports with the kernelSimon Glass2015-08-05-89/+94
| | | | | | | | | | | | | | | | The kernel uses upper case for I2C unit addresses. Follow the same convention to reduce differences. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* | ARM: tegra: Add p2371-0000 boardStephen Warren2015-08-06-0/+69
| | | | | | | | | | | | | | | | | | | | | | P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add e2220-1170 boardStephen Warren2015-08-06-0/+67
| | | | | | | | | | | | | | | | | | E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various expansion modules. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: enable GPU DT node when appropriateAlexandre Courbot2015-08-06-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T124/210 requires some specific configuration (VPR setup) to be performed by the bootloader before the GPU can be used. For this reason, the GPU node in the device tree is disabled by default. This patch enables the node if U-boot has performed VPR configuration. Boards enabled by this patch are T124's Jetson TK1 and Venice2 and T210's P2571. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: move VPR configuration to a later stageAlexandre Courbot2015-08-06-18/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot is responsible for enabling the GPU DT node after all necessary configuration (VPR setup for T124) is performed. In order to be able to check whether this configuration has been performed right before booting the kernel, make it happen during board_init(). Also move VPR configuration into the more generic gpu.c file, which will also host other GPU-related functions, and let boards specify individually whether they need VPR setup or not. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: restrict usable RAM size furtherStephen Warren2015-08-06-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, ARM64 devices typically run a secure monitor in EL3 and U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3 code and data. These carve-outs are located at the top of 32-bit address space. Restrict U-Boot's RAM usage to well below the location of those carve-outs. Ideally, we would the secure monitor would inform U-Boot of exactly which RAM it could use at run-time. However, I'm not sure how to do that at present (and even if such a mechanism does exist, it would likely not be generic across all forms of secure monitor). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.Tom Warren2015-08-05-174/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: clocks: Add 38.4MHz OSC support for T210 useTom Warren2015-08-05-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs to be measured - should be close to 700MHz (1.4G/2). Note that some freqs aren't in the PLLU table in T210 TRM (13, 26MHz), so I used the 12MHz table entry for them. They shouldn't be selected since they're not viable T210 OSC freqs. Since there are now 2 new OSC defines, all tables (pll_x_table, PLLU) had to increase by two entries, but since 38.4/48MHz are not viable osc freqs on T20/30/114, etc, they're just set to 0. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | T210: P2571: Turn CPU fan onTom Warren2015-08-05-0/+3
|/ | | | | | | | CPU board (E2530) has a fan - turn it on via GPIO to keep the SoC cool. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* sunxi: Drop our own copy of the USB_KEYBOARD optionsHans de Goede2015-08-05-0/+1
| | | | | | | USB_KEYBOARD is now defined in drivers/usb/Kconfig, drop our own duplicate definition. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSBPaul Kocialkowski2015-08-05-2/+2
| | | | | | | | | USB-related options are usually prefixed with CONFIG_USB and platform-specific adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* armv8/lsch3/config: Define USB XHCI controller base address for LS2085ANikhil Badola2015-08-03-0/+3
| | | | | | | | Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085ANikhil Badola2015-08-03-0/+1
| | | | | | | | Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin tableWang Dongsheng2015-08-03-0/+8
| | | | | | | | | | | Bootrom will put cpus into WFE state when boot cpu release cpus, so target cpu cannot correctly go to spin state. Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target cpu can fall into u-boot spin table. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-218/+1776
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| * imx: mx6ul_14x14_evk add basic board supportPeng Fan2015-08-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add dram spl configuration and header filePeng Fan2015-08-02-10/+141
| | | | | | | | | | | | | | | | | | | | | | | | 1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/ULPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6) Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul update soc related settingsPeng Fan2015-08-02-5/+4
| | | | | | | | | | | | | | | | 1.Update WDOG settings. 2.No need to gate/ungate all PFDs for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6ul select SYS_L2CACHE_OFFPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | | | | | i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. There is on specific switch for on/off L2 Cache, so default select SYS_L2CACHE_OFF. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add clock supportPeng Fan2015-08-02-90/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx-common: timer: add i.MX6UL supportPeng Fan2015-08-02-3/+5
| | | | | | | | | | | | Add i.MX6UL GPT timer support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6ULPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul: Update imx registers head filePeng Fan2015-08-02-25/+35
| | | | | | | | | | | | | | | | | | | | | | | | 1. Update imx register base address for i.MX6UL. 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE. 3. Remove #ifdef for register addresses that equal to "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips. 4. According fuse map, complete fuse_bank4_regs. 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX, because we can use runtime check Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul: Add pins IOMUX head filePeng Fan2015-08-02-0/+1067
| | | | | | | | | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-11-15 16:41:14 +0000