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* ARM: atmel: sama5d4: add bus matrix init functionBo Shen2015-02-07-0/+35
| | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: atmel: sama5d4: add matrix1 base addr definitionBo Shen2015-02-07-0/+2
| | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: atmel: spl: can not disable osc for sama5d4Bo Shen2015-02-07-0/+2
| | | | | | The SAMA5D4 SoC on chip rc oscillator can not be disabled. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: atmel: spl: add saic to aic redirect functionBo Shen2015-02-07-0/+8
| | | | | | | Some SoC need to redirect the saic to aic to make the interrupt to work, here add a weak function to be replaced by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: atmel: spl: add weak bus matrix init functionBo Shen2015-02-07-0/+7
| | | | | | | Some SoC need to configure the bus matrix, add an weak function to be replace by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* ARM: atmel: sama5: add sfr register header fileBo Shen2015-02-07-0/+38
| | | | | | | | | The SFR (special function registers) can be shared bwteen sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adoptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: sama5: add bus matrix header fileBo Shen2015-02-07-0/+37
| | | | | | | | This matrix header file can be shared between sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adaptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: atmel: clock: make it possible to configure HMX32Bo Shen2015-02-07-0/+8
| | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2015-02-02-47/+227
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| * davinci: Do not duplicate setting of gdTom Rini2015-01-29-16/+1
| | | | | | | | | | | | | | | | | | | | In f0c3a6c we stopped setting gd in board_init_f, but later had to revert to due problems on certain platforms. As davinci does not look to have these problems, we can drop the setting here and rely upon crt0.S to do it. Cc: Peter Howard <pjh@northern-ridge.com.au> Signed-off-by: Tom Rini <trini@ti.com>
| * omap3: add some MUX definitions for upcoming cairoAlbert ARIBAUD \(3ADEV\)2015-01-29-2/+49
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: mmc: add 1.8v bias setting for MMC1Albert ARIBAUD \(3ADEV\)2015-01-29-0/+1
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: add SDRC settings for Samsung K4X51163PGAlbert ARIBAUD \(3ADEV\)2015-01-29-0/+43
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: make SDRC SHARING setting configurableAlbert ARIBAUD \(3ADEV\)2015-01-29-1/+6
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * omap3: enable GP9 timer and UART2Albert ARIBAUD \(3ADEV\)2015-01-29-0/+9
| | | | | | | | | | | | These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-29-28/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2015-02-02-7/+39
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| * | sunxi: rsb: Move rsb_set_device_mode() call to rsb_init()Hans de Goede2015-02-02-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | It turns out that the device_mode_data is rsb specific, rather then slave specific, so integrate the rsb_set_device_mode() call into rsb_init(). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi: rsb: Add sun9i (A80 support)Hans de Goede2015-02-02-2/+25
| | | | | | | | | | | | | | | | | | | | | Add support for the A80 to the rsb code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig optionHans de Goede2015-02-02-0/+4
| |/ | | | | | | | | | | | | | | And use this to set the GMAC Transmit Clock Delay Chain value on Banana boards, rather then keying of CONFIG_TARGET_FOO. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2015-01-30-163/+203
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| * | dm: exynos: dts: Set the offset length for cros_ecSimon Glass2015-01-29-0/+1
| | | | | | | | | | | | | | | | | | The EC has no concept of offset, so use a value of 0. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | odroid u3: dts: add missing i2c aliasesPrzemyslaw Marczak2015-01-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This change fixes i2c bus numbering for Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos5: pinmux: check flag for i2c configPrzemyslaw Marczak2015-01-29-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some versions of Exynos5 supports High-Speed I2C, on few interfaces, this change allows support this. The new flag is: PINMUX_FLAG_HS_MODE Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | arndale: dts: add missing i2c aliasesPrzemyslaw Marczak2015-01-29-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this alias setting, the seq numbers of the i2c devices are wrong. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos4: dts: add missing i2c propertiesPrzemyslaw Marczak2015-01-29-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modify i2c nodes in exynos4.dtsi with: - adding proper interrupts arrays for each i2c node, which allows to decode periph id - add reg address for each i2c node for i2c driver internal use Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * | dm: i2c: Provide an offset length parameter where neededSimon Glass2015-01-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * | dm: exynos: dts: Use GPIO bank phandles for GPIOsSimon Glass2015-01-29-39/+30
| | | | | | | | | | | | | | | | | | | | | | | | U-Boot now supports using GPIOs using bank phandles instead of global numbers. Update the exynos device tree files to use this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOsSimon Glass2015-01-29-85/+109
| | | | | | | | | | | | | | | | | | This new method is much easier and matches the kernel. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-3/+4
| | | | | | | | | | | | | | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: zynq: Remove inline gpio functionsSimon Glass2015-01-29-15/+0
| | | | | | | | | | | | | | | | | | | | | These functions serve no useful purpose, and conflict with the generic API. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: tegra: video: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-4/+5
| |/ | | | | | | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: armv7 fix spelling of SCTRLPeng Fan2015-01-30-4/+4
| | | | | | | | | | | | | | SCTLR is the abbreviation of System Control Register, so we should use SCTLR but not SCTRL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | vexpress64: support the Juno Development PlatformLinus Walleij2015-01-30-0/+4
| | | | | | | | | | | | | | | | | | | | The Juno Development Platform is a physical Versatile Express device with some differences from the emulated semihosting models. The main difference is that the system is split in a SoC and an FPGA where the SoC hosts the serial ports at totally different adresses. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | vexpress64: get rid of CONFIG_SYS_EXTRA_OPTIONSLinus Walleij2015-01-30-1/+13
|/ | | | | | | | | | | | | | | | | | | | The Versatile Express ARMv8 semihosted FVP platform is still using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure some compile-time flags. Get rid of this and create a Kconfig entry for the FVP model, and a selectable bool for the semihosting library. The FVP subboard is now modeled as a target choice so we can eventually choose between different ARMv8 versatile express boards (FVP, base model, Juno...) this way. All dependent symbols are updated to reflect this. The 64bit Versatile Express board symbols are renamed VEXPRESS64 so we have some chance to see what is actually going on. Tested on the FVP fast model. Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-1/+21
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| * ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * ARM: atmel: sama5d4: add usb platform dataBo Shen2015-01-19-1/+1
| | | | | | | | | | | | The SAMA5D4 has the same usb platform data with SAMA5D3 SoC. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-26-5/+51
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| * | ARM: zynq: List qspi, smc and nand baseaddressesMichal Simek2015-01-26-0/+3
| | | | | | | | | | | | | | | | | | Add missing addresses to the list. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: List nand, qspi and jtag boot modesMichal Simek2015-01-26-0/+11
| | | | | | | | | | | | | | | | | | Use full boot mode list in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: slcr: Dont modify the reserved bitsSiva Durga Prasad Paladugu2015-01-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: ddrc: Setup half of memory only for ECC caseMichal Simek2015-01-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup half of memory from ram_size for ECC case. All the time the same board can be configured with or without ECC. Based on ECC case detection use half of memory with the same configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Remove empty lineMichal Simek2015-01-26-1/+0
| | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Enable the Neon instructionsMichal Simek2015-01-26-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the lowlevel_init to enable the Neon instructions. Initially the u-boot was causing undefined instruction exception if loaded through tcl, and working fine if loaded through FSBL. The exception was causing in convertion formula of given time to ticks. It was because, the Neon instructions were disabled and hence causing the undefined exception. In FSBL case, the FSBL was enabling the Neon instructions. Hence, added the lowlevel_init to enable the Neon instructions. Also enable neon instructions for non-xilinx toolchain. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-marvellTom Rini2015-01-25-3/+8
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| * | | ARM: kirkwood: fix cpu info for 6282 device idLuka Perkov2015-01-25-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Luka Perkov <luka@openwrt.org> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Stefan Roese <sr@denx.de>
* | | | fsl/ls1021qds: Add deep sleep supporttang yuantian2015-01-24-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD bootAlison Wang2015-01-23-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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