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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-1219/+9426
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| * arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the READMELucas Stach2013-02-11-1/+1
| | | | | | | | | | | | | | | | | | No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com>
| * Tegra114: Dalmore: Add DT filesTom Warren2013-02-11-0/+5
| | | | | | | | | | | | | | | | These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra114: Add common CPU (shared) filesTom Warren2013-02-11-4/+1291
| | | | | | | | | | | | These files are used by both SPL and main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra114: Add CPU (armv7) filesTom Warren2013-02-11-0/+59
| | | | | | | | | | | | | | | | These files are for code that runs on the CPU (A15) on T114 boards. At this time, there is no A15-specific code here. As T114-specific run-time code is added, it'll go here. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra114: Add AVP (arm720t) filesTom Warren2013-02-11-38/+403
| | | | | | | | | | | | | | This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra114: Add arch-tegra114 include filesTom Warren2013-02-11-5/+1365
| | | | | | | | | | | | | | | | | | | | Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * tegra: add SPI SLINK driverAllen Martin2013-02-11-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add addresses of SPI SLINK controllersAllen Martin2013-02-11-0/+6
| | | | | | | | | | | | | | | | Add I/O addresses of SPI SLINK controllers 1-6 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra30: fdt: add SPI SLINK nodesAllen Martin2013-02-11-0/+72
| | | | | | | | | | | | | | | | Add tegra30 SPI SLINK nodes to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra30: add SBC1 to periph id mapping tableAllen Martin2013-02-11-1/+1
| | | | | | | | | | | | | | | | SBC1 is SPI controller 1 on tegra30 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra20: fdt: add SPI SFLASH nodeAllen Martin2013-02-11-0/+12
| | | | | | | | | | | | | | Add node for tegra20 SPI SFLASH controller to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: rename FUNCMUX_UART2_UARTBStephen Warren2013-02-11-4/+4
| | | | | | | | | | | | | | | | | | FUNCMUX_ defines should be named after the pin groups they affect, not after the module they're muxing onto those pin groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.cTom Warren2013-02-11-1188/+768
| | | | | | | | | | | | | | | | | | This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entryTom Warren2013-02-11-8/+0
| | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Add DDR3 support for AM335x-EVM (Version 1.5A)Jeff Lance2013-02-07-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the DDR3 chip. [Hebbar Gururaja <gururaja.hebbar@ti.com>] - Resolve merge conflict while rebasing. File structure is changed in the mainline. So re-arrange the code accordingly. - Update commit message to reflect the DDR3 part number Signed-off-by: Jeff Lance <j-lance1@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
| * pcm051: Add support for Phytec phyCORE-AM335xLars Poeschel2013-02-07-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board is named pcm051 and has this hardware: SOC: TI AM3359 DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB ETH 1: LAN8710AI SPI-Flash: W25Q64BVSSIG RTC: RV-4162-C7 I2C-EEPROM: CAT32WC32 NAND: MT29F4G08_VFPGA63 PMIC: TPS65910A3 LCD Supported: UART 1 MMC/SD ETH 1 USB I2C SPI Not yet supported: NAND RTC LCD Signed-off-by: Lars Poeschel <poeschel@lemonage.de> [trini: Add #define CONFIG_PHY_ADDR 0 to config] Signed-off-by: Tom Rini <trini@ti.com>
| * am33xx: add a pulldown macro to pinmux configLars Poeschel2013-02-07-1/+2
| | | | | | | | Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
| * ARM: add wfi assembly macroRob Herring2013-02-03-0/+6
| | | | | | | | | | | | | | Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-02-02-70/+1435
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| | * mxs: mmc: Allow overriding default card detect implementationMarek Vasut2013-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some MXS based boards do not implement the card-detect signal. Allow user to specify alternate card-detect implementation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: ssp: Add SSP registers map for MX23Marek Vasut2013-01-28-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 SSP register layout differs from MX28 in certain bits, adjust the register layout accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: dma: Fix APBH DMA driver for MX23Marek Vasut2013-01-28-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 has less channels for the APBH DMA, sligtly different register layout and some bits in those registers are placed differently. Reflect this in the driver. This patch fixes MMC/DMA issue on MX23. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: Use __weak annotation to simplify codeFabio Estevam2013-01-28-7/+4
| | | | | | | | | | | | | | | | | | | | | Using the __weak annotation can make the code cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mxs: Boost the memory power supplyMarek Vasut2013-01-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory power supply on MX23 didn't pump out enough juice into the DRAM chip, thus caused occasional memory corruption. Fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * imximage.cfg: run files through C preprocessorTroy Kisky2013-01-22-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The '#' used as comments in the files cause the preprocessor trouble, so change to /* */. The mkimage command which uses this preprocessor output was moved to arch/arm/imx-common/Makefile .gitignore was updated to ignore .cfgtmp files. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| | * mxs: Add MX23 quirks into the clock codeOtavio Salvador2013-01-21-11/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: Fix the memory init for MX23Otavio Salvador2013-01-21-15/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory init is slightly different on MX23, thus split the memory init for mx23 and mx28 into different functions. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: Add function to ungate the power block on MX23Marek Vasut2013-01-21-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power block on MX23 must first be ungated before it can be operated. Add function to MXS power init that ungates it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: config: Enable building of u-boot.sb binaryOtavio Salvador2013-01-21-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | For i.MX23 we need to pass imx23 as elftosb param. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: SPL: Initialize DDR at 133MHzOtavio Salvador2013-01-21-0/+20
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: SPL: Add boot mode supportOtavio Salvador2013-01-21-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the boot mode support for i.MX23 processors. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add boot mode descriptionOtavio Salvador2013-01-21-0/+12
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add support on print_cpuinfo()Otavio Salvador2013-01-21-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add information to identify i.MX23 chips and its known revisions. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: ssp: Fix ssp-regs.h for MX23Marek Vasut2013-01-21-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Disable SSP2 and SSP3 ports on MX23. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add POWER and CLKCTRL register definitionsMarek Vasut2013-01-21-1/+585
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add register definitions for the i.MX23 power control block and clock control block. These are essential for the basic bootstrap of the i.MX23. Also, properly include them in imx-regs.h . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add iomux-mx23.hOtavio Salvador2013-01-21-0/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | | This has been copied from Linux source at revision 786f02b719f. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add register base addressesOtavio Salvador2013-01-21-5/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the base addresses of i.MX23 and easy the detection of wrong order in board setup, in case no SoC has been set, an error is raised during build. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: clock: Use 'mxs' prefix for methodsOtavio Salvador2013-01-21-26/+26
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: ssp: Pull out the SSP bus to regs conversionMarek Vasut2013-01-21-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create function which converts SSP bus number to SSP register pointer. This functionality is reimplemented multiple times in the code, thus make one common implementation. Moreover, make it a switch(), since the SSP ports are not mapped in such nice linear fashion on MX23, therefore having it a switch will simplify things there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | tegra: fdt: add apbdma nodeAllen Martin2013-01-17-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | Add apbdma node for tegra20 and tegra30, copied directly from tegra Linux dtsi files. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: fdt: sort dts filesAllen Martin2013-01-17-189/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort nodes in dts files according the the following rules: 1) Any nodes that already exist in any /include/d file, in the order they appear in the /include/d file. 2) Any nodes with a reg property, in order of their address. 3) Any nodes without a reg property, alphabetically by node name. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: fdt: remove clocks nodesAllen Martin2013-01-17-20/+0
| | | | | | | | | | | | | | | | | | | | | These nodes are unused. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: remove IRDA pinmux synonymAllen Martin2013-01-16-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this synonym and replace with UARTB to disambiguate. Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra30: fdt: Update DT files with I2C info for T30/CardhuTom Warren2013-01-16-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note that T30 does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but DVC_I2C is still used to designate the controller intended for power control (PWR_I2C in the schematics). On Cardhu, it's used to access the PMU and EEPROM, as well as the audio codec, temp sensor, and fuel gauge devices from the OS. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra30: clocks: Fix clock tables for I2C and other periphsTom Warren2013-01-16-34/+48
| | | | | | | | | | | | | | | | | | | | | Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra30: Add generic Tegra30 build supportTom Warren2013-01-16-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic Tegra30 (T30) build support - no specific board is targeted. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | Tegra30: Cardhu: Add DT filesTom Warren2013-01-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | Tegra30: Add common CPU (shared) filesTom Warren2013-01-16-56/+1768
| | | | | | | | | | | | | | | | | | | | | | | | | | | These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | Tegra30: Add CPU (armv7) filesTom Warren2013-01-16-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | These files are for code that runs on the CPU (A9) on T30 boards. At this time, there are no T30-specific ARMV7 files. As T30-specific run-time code is added, it'll go here. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidai.com>
generated by cgit v1.1 at 2024-12-21 12:22:37 +0000