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* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-04-13-48/+100
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| * imx: mx7d: move MX7D to Kconfig entryPeng Fan2016-03-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to "select MX7D" to boards using i.MX7 Dual. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: mx6sx: move MX6SX to Kconfig entryPeng Fan2016-03-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to "select MX6SX" to boards using i.MX6 SoloX. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: mx6: Add CCV xPress board supportStefan Roese2016-03-26-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for the CCV xPress board which is equipped with the i.MX6UL. And provides the following interfaces: - 128MiB DDR - UART - I2C - eMMC (with booting) - Ethernet - USB This patch adds two build targets. One with and one without SPL. The non-SPL version is used for loading U-Boot via USB (imx_usb_loader). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * arm: mx6: Add UART8 base address for i.MX6ULStefan Roese2016-03-26-0/+1
| | | | | | | | | | | | | | | | | | Add the base address for the i.MX6UL so that this UART can be used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * warp7: Add initial supportFabio Estevam2016-03-26-0/+7
| | | | | | | | | | | | | | | | | | | | | | Add the basic support for Warp7 board. For more information about this reference design, please visit: https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * mx27: 16-bit wide watchdog registersLeonid Iziumtsev2016-03-25-7/+7
| | | | | | | | | | | | | | Make the watchdog registers 16-bit wide, as they are according to TRM. Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: imx6: Switch DDR3 calibration to wait_for_bit()Marek Vasut2016-03-25-32/+12
| | | | | | | | | | | | | | | | | | Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit() to generic implementation of wait_for_bit(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx: print ARM clock for clocks commandPeng Fan2016-03-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Default print ARM clock for clocks command. Test on i.MX6UL 14x14 evk board: " => clocks PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz ARM 396000 kHz " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6ul configure the PMIC_STBY_REQ pin as open drainPeng Fan2016-03-25-1/+11
| | | | | | | | | | | | | | | | | | Configure the PMIC_STBY_REQ pin as open drain 100K according to the design team's requirement for the PMIC_STBY_REQ pin for i.MX 6UltraLite TO1.0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6ul: skip setting ahb ratePeng Fan2016-03-25-7/+12
| | | | | | | | | | | | | | | | To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6: Fix incorrect clear mmdc_ch0 handshake maskYe Li2016-03-25-1/+4
| | | | | | | | | | | | | | | | | | | | | | Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * Merge branch 'next'Stefano Babic2016-03-20-0/+34
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| | * mx7: Distinguish between dual and solo versionsFabio Estevam2016-03-09-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the number of cores in the fuses to distinguish between the dual and solo versions. Tested on a mx7d sabresd and on a mx7solo warp7. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| | * arm: imx: Add support for GE Bx50v3 boardsAkshay Bhat2016-03-09-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for GE B450v3, B650v3 and B850v3 boards. The boards are based on Advantech BA16 module which has a i.MX6D processor. The boards support: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-04-12-0/+1
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| * | | arm: mvebu: Add base address for 2nd I2C controllerStefan Roese2016-04-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MVEBU_TWSI1_BASE define so that the 2nd I2C controller on e.g. AXP can be used. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | sunxi: Add defconfig and dts file for Orange Pi One SBCHans de Goede2016-04-12-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Orange Pi One SBC, is a stripped down version of the popular Orange Pi PC. The one is a H3 based SBC, with 512M of RAM, micro-sd slot, 1 host usb, 1 otg usb, hdmi and 100Mbit ethernet. The dts is identical to the dts submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | sunxi: Enable CMD_GPIO on all sunxi boardsHans de Goede2016-04-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have CONFIG_CMD_GPIO=y in almost all sunxi boards, but after its Kconfig conversion it has ended up missing on some recently added boards. Simply select it for ARCH_SUNXI, so that we get it on all sunxi boards for both a consistent user experience and simpler defconfig files. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | sunxi: Enable usb ports on the Sinovoip BPI M3Hans de Goede2016-04-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DLDO3 is used to provide Port-D power and PD is used for the usb-hub / sata-5v enable pins. The 2.5V comes from the schematic and matches the factory image fex file. The dts changes are the minimal changes needed for u-boot to pick-up the usb host controllers. The upstream kernel does not (yet) have usb host support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | sunxi: Add INITIAL_USB_SCAN_DELAY Kconfig optionHans de Goede2016-04-12-0/+7
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | Some boards have on board usb devices which need longer than the USB spec's 1 second to connect from board powerup. Add a config option which when non 0 adds an extra delay before the first usb bus scan. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with asm codeHans de Goede2016-04-11-96/+74
| | | | | | | | | | | | | | | | | | | | | Lets be consistent and also replace v7_maint_dcache_all() with asm code for the invalidate case. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) with asm codeHans de Goede2016-04-11-102/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v7_maint_dcache_all() does not work reliable when build with gcc6, see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788 While debugging this I learned that v7_maint_dcache_all() is unreliable when build with gcc5 too when it is marked as noinline. This commit fixes the reliability issues by replacing the C-code with the ready to use asm implementation from the kernel. Given that this code when written as C-code clearly is quite fragile (also see the existing comments about the C-code being the way it is to get optimal assembly) and that we have a proven asm alternative, I believe that this is the best solution. Note that we actually already had a copy of the kernel's v7_flush_dcache_all() before this commit in arch/arm/mach-uniphier/arm32/lowlevel_init.S. This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper which saves / restores the clobbered registers for use from C-code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | am33xx changed BOOT_DEVICE_SPI to correct valueVogt, Christof2016-04-11-1/+1
| | | | | | | | | | | | | | | | | | | | | Changed BOOT_DEVICE Code for SPI on AM33xx. According AM335x reference manual page 4960 (SPRUH73L-October 2011-Revised February 2015) Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | rpi: remove redundant board filesStephen Warren2016-04-11-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that rpi_*defconfig and Kconfig (rather than the config header file) provide the identity of the build, we don't need to separate config headers and board directories for each RPi variant. Set CONFIG_SYS_BOARD and CONFIG_SYS_CONFIG_NAME so that we can get rid of the duplication. This requires a tiny number of extra ifdefs in the config header. The only disadvantage of this approach is that the $board/$board_name environment variables aren't as descriptive as they used to be. This isn't really an issue because those only exist to allow scripts to create DTB filenames at runtime. However, the RPi board code already sets $fdtfile to something more accurate based on FW-reported board ID anyway. While at it, unify some Kconfig select options, and add a MAINTAINERS entry for bcm283x too. Partially-suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: rpi: add some missing Kconfig help textStephen Warren2016-04-11-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | Add notes re: enabling the UART to the RPi 3 32-bit help text. Fully describe the RPi 3 64-bit board option. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: add Raspberry Pi 3 64-bit configStephen Warren2016-04-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On all Pis so far, the VC FW provides a short stub to set up the ARM CPU before entering the kernel (a/k/a U-Boot for us). This feature is not currently supported by the VC FW when booting in 64-bit mode. However, this feature will likely appear in the near future, and this U-Boot port assumes that such a feature is in place. Without that feature, or a temporary workaround described below, U-Boot will not boot. Once the VC FW does provide the ARM stub, u-boot.bin built for rpi_3 can be used drectly as kernel7.img, in the same way as any other RPi port. The following config.txt is required: # Fix mini UART input frequency, and setup/enable up the UART. # Without this option, U-Boot will not boot, even if you don't care # about the serial console. This option will always be required for # all RPi3 use-cases, unless the PL011 UART is used, which is not # yet supported by rpi_3* builds of U-Boot. enable_uart=1 # Boot in AArch64 (64-bit) mode. # It is possible that a future VC FW will remove the need for this # option, instead auto-setting 32-/64-bit mode based on the "kernel" # filename present on the SD card. arm_control=0x200 Prior to the VC FW providing the ARM boot stub, you can use the following steps to build an equivalent stub into the U-Boot binary: git clone https://github.com/swarren/rpi-3-aarch64-demo.git \ ../rpi-3-aarch64-demo (cd ../rpi-3-aarch64-demo && ./build.sh) Build U-Boot for rpi_3 in the usual way cat ../rpi-3-aarch64-demo/armstub64.bin u-boot.bin > u-boot.bin.stubbed Use u-boot.bin.stubbed as kernel7.img on the Pi SD card. In this case, the following additional entries are required in config.txt: # Tell the FW to load the kernel image at address 0, the reset vector. kernel_old=1 Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: allow CONFIG_GICV* not to be definedStephen Warren2016-04-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | There are ARM SoCs (such as the BCM2837) do not contain an ARM GIC. Fix the ARMv8 CPU startup code to compile in this case. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-04-10-16/+36
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| * | | arm: socfpga: Nuke useless includeMarek Vasut2016-04-10-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmmc.h include was forgotten during the migration of dwmmc probing to DM. Since the shiny DM is in place now, remove this relic of the past. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | | arm: socfpga: Handle phy-mode OF property for GMACsMarek Vasut2016-04-10-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thus far, the socfpga init code had hard-coded the configuration of the ethernet PHY interface to RGMII in the ethernet registers in sysmgr space, so PHYs connected in another modes did not work. This patch fixes support for configurations where the ethernet PHYs are connected over MII/GMII/RMII interfaces by parsing the phy-mode OF property of the GMACs and configuring the ethernet registers in sysmgr space accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Reported-by: Denis Bakhvalov <denis.bakhvalov@nokia.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | | arm: add missing writes[bwql], reads[bwql].Purna Chandra Mandal2016-04-10-0/+7
|/ / / | | | | | | | | | | | | | | | | | | ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h but not the writes[bwql], reads[bwql] needed by some drivers. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-04-06-35/+62
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| * | | armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-28/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arm: ls102xa: Fix order of CSU indexes in ns_access.hVincent Siles2016-04-06-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aims to fix the order of CSU slave index for the LS1021a board. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: LSCH2 early and final mmu needs matching NS attributeEd Swarthout2016-04-06-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching between the early and final mmu tables, the stack will get corrupted if the Non-Secure attribute is different. For ls1043a, this issue is currently masked because flush_dcache_all is called before the switch when CONFIG_SYS_DPAA_FMAN is defined. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | spi: kirkwood_spi: Add support for multiple chip-selects on MVEBUStefan Roese2016-04-06-5/+12
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-04-04-9/+8
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| * | | ARM64: zynqmp: Select SYS_CONFIG_NAME via KconfigMichal Simek2016-04-04-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option enable adding new platform suport just by adding defconfig and DTS file which will target generic configuration for SoC. Make no sense to extend Kconfig just create a pointer between DTS and configuration file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: gem: Allow to set the MAC from an EEPROMJoe Hershberger2016-04-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: mvebu: Don't enable d-cache on A375Stefan Roese2016-04-04-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada 375 still has some problems with d-cache enabled in the ethernet driver (mvpp2). So lets keep the d-cache disabled until this is solved. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | | arm: mvebu: Add basic support for Armada 375 eval board db-88f6720Stefan Roese2016-04-04-2/+887
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell A375 eval board. Tested are the following interfaces: - I2C - SPI - SPI NOR - Ethernet (mvpp2), port 0 & 1 Currently the A375 SerDes and DDR3 init code is not intergrated. So the SPL U-Boot is not fully functional. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | | arm: mvebu: Add basic support for the Marvell Armada 375 SoCStefan Roese2016-04-04-5/+92
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Armada 375. Please note that currently the SerDes and DDR3 init code for the A375 is not included / enabled. This will be done in a later, follow-up patch. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | board: Add Qualcomm Dragonboard 410C supportMateusz Kulikowski2016-04-01-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification. Features (present out of the box): - 4x Cortex A53 (ARMv8) - 2x USB Host port - 1x USB Device port - 4x LEDs - 1x HDMI connector - 1x uSD connector - 3x buttons (Power, Vol+, Vol-/Reset) - WIFI, Bluetooth with integrated antenna - 8GiB eMMC U-Boot boots chained with fastboot in 64-bit mode. For detailed build instructions see readme.txt in board directory. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | arm: Add support for Qualcomm Snapdragon familyMateusz Kulikowski2016-04-01-0/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code: - Reset controller (PSHOLD) - Clock controller (very simple clock configuration for MMC and UART) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | sniper: Change vendor name from lge to lg, matching devicetree vendor prefixPaul Kocialkowski2016-04-01-1/+1
| | | | | | | | | | | | | | | | | | | | | This moves the sniper board from the lge to lg, in order to match the devicetree vendor prefix already defined in the kernel. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | arm: spl: Align default board_init_f comment with codeAndreas Dannenberg2016-04-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The default board_init_f() implementation performs a call to board_init_r() as the last step of the sequence. Fix the comment for this function to reflect the actual execution flow. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* | | rpi: BCM2837 and Raspberry Pi 3 32-bit supportStephen Warren2016-04-01-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with the CPU complex swapped out for a quad-core ARMv8. This can operate in 32- or 64-bit mode. 32-bit mode is the current default selected by the VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of U-Boot for the Raspberry Pi 3. >From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a change in usage of the SoC UARTs. On all previous Pis, the PL011 was the only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a UART to connect to the SoC. By default, the PL011 is used for this purpose since it has larger FIFOs than the other "mini" UART. However, this can be configured via the VideoCore firmware's config.txt file. This patch hard-codes use of the mini UART in the RPi 3 port. If your system uses the PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot port instead. A future change might determine which UART to use at run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed together. The mini UART has some limitations. One externally visible issue in the BCM2837 integration is that the UART divides the SoC's "core clock" to generate the baud rate. The core clock is typically variable, and under control of the VideoCore firmware for thermal management reasons. If the VC FW does modify the core clock rate, UART communication will be corrupted since the baud rate will vary from the expected value. This was not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To work around this, the VideoCore firmware can be told not to modify the SoC core clock. However, the only way this can happen and be thermally safe is to limit the core clock to a low/minimum frequency. This leaves performance on the table for use-cases that don't care about a UART console. Consequently, use of the mini UART console must be explicitly requested by entering the following line into config.txt: enable_uart=1 A recent version of the VC firmware is required to ensure that the mini UART is fully and correctly initialized by the VC FW; at least firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: bcm2835: expand Kconfig target descriptionsStephen Warren2016-04-01-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | This adds an explanation of which Raspberry Pi models each target option supports. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: bcm2835: move CONFIG_BCM283* to KconfigStephen Warren2016-04-01-1/+11
| | | | | | | | | | | | | | | Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-12-12 19:52:14 +0000