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* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-6/+57
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| * arm:mx6sx add QSPI supportPeng Fan2014-12-31-6/+57
| | | | | | | | | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-7/+2693
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| * | ARM: Implement non-cached memory supportThierry Reding2014-12-18-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on Jetson TK1Thierry Reding2014-12-18-0/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes the second root port to a miniPCIe slot. Enable the PCIe controller and the network driver to allow the device to boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra124 PCIe device tree nodeThierry Reding2014-12-18-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra124 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add GIC for Tegra124Thierry Reding2014-12-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC v2 found on the Cortex-A15 CPU complex of Tegra124. U-Boot doesn't use this but subsequent patches will add device tree nodes that reference it by phandle. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on BeaverThierry Reding2014-12-18-0/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Beaver has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. In addition the board has a mini-PCIe expansion slot. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on CardhuThierry Reding2014-12-18-0/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC is available on the dock over the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra30 PCIe device tree nodeThierry Reding2014-12-18-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra30 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add GIC for Tegra30Thierry Reding2014-12-18-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use it directly but subsequent patches will add device tree nodes that reference it by phandle. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on TrimSliceThierry Reding2014-12-18-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra20 PCIe device tree nodeThierry Reding2014-12-18-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra20 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable XUSB pad controller on Jetson TK1Thierry Reding2014-12-18-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PCIe and SATA lane configuration to the Jetson TK1 device tree, so that the XUSB pad controller can be appropriately configured. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add XUSB pad controller on Tegra124Thierry Reding2014-12-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA lanes. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement XUSB pad controllerThierry Reding2014-12-18-0/+781
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement powergate supportThierry Reding2014-12-18-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the powergate API that allows various power partitions to be power up and down. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Provide PCIEXCLK reset IDThierry Reding2014-12-18-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement tegra_plle_enable()Thierry Reding2014-12-18-0/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: colibri_t30: comment style fixMarcel Ziswiler2014-12-18-4/+8
| |/ | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-30-1/+11
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| * | arm: socfpga: Change watchdog timeoutStefan Roese2014-12-21-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current current watchdog timeout of 12 seconds is a bit small for booting into Linux, especially when using a NFS based rootfs. So lets change this timeout to a more defensive value of 30 seconds. Also we now call the hw_watchdog_init() function so that we override the value already configured from the Preloader. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-30-18/+13
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| * | | imx: i2c: Zap unnecessary malloc() callsMarek Vasut2014-12-30-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The malloc() calls are unnecessary, just allocate the stuff on stack. While at it, reorder the code a little, so that only one variable is used for the text, use snprintf() instead of sprintf() and use %01d as a formatting string to avoid any possible overflows. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | | imx SPL: enable boot from eMMC boot partitions.Pierre Aubert2014-12-30-1/+3
| | | | | | | | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
| * | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2014-12-30-116/+168
| |\ \ \ | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | | imx:mx6 fix return value of mxc_get_clockPeng Fan2014-12-19-1/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mxc_get_clock's return type is unsigned int. 'return -1' is same with 'return 0xffffffff', so 0 should be used as the return value when unsupported mxc_clock type is passed to mxc_get_clock. Also include an err message when unsupported mxc_clock type is passed to mxc_get_clock. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-12-30-3/+826
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| * | | | ARM: UniPhier: display boot swap pin status by pinmon commandMasahiro Yamada2014-12-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This information would be useful enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add dump command of DDR PHY parametersMasahiro Yamada2014-12-30-0/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a dump command of DDR PHY parameters of UniPhier SoC family. It might not be used very often for the regular operation but it would be useful when something goes wrong with DDR memories. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add DDR PHY training codeMasahiro Yamada2014-12-30-3/+586
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | This training code provides run-time adjustment of DDR PHY parameters for stable DDR operation. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2014-12-30-9/+57
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| * | | arm: exynos: clock: support SPLL as mmc source clock for exynos5420Joonyoung Shim2014-12-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC of exynos5420 can select SPLL as source clock, so add to support SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | odroid-XU3: Add entry for DTS EHCI GPIOSjoerd Simons2014-12-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add samsung,vbus-gpio information for the XU3. This allows the usage of the EHCI controller on the XU3, which is connected to the SMSC LAN9514 chip (usb hub + network). Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | exynos5420: fix compilation without parade videoSjoerd Simons2014-12-22-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all exynos 5420 based devices with an LCD also have a parade LVDS bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled and CONFIG_VIDEO_PARADE is not. As a side-effect move the parade functions from the exynos system header file to its own file. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Exynos5800: The Peach-Pi board does not have a Parade video bridgeSjoerd Simons2014-12-22-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the Pi. So drop it from device-tree Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang2014-12-22-1/+51
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | bcm281xx: add support for "USB OTG clock"Steve Rae2014-12-29-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
* | | ARM: rpi: support model A+Stephen Warren2014-12-29-0/+1
| | | | | | | | | | | | | | | | | | | | | Add a board rev entry for the new model A+, and augment the board rev error handling code to be a bit more verbose. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | arm: semihosting: get rid of forward declarationsLinus Walleij2014-12-29-89/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By rearranging the functions in the semihosting code we can avoid forward-declaration of the internal static functions. This puts the stuff in a logical order: read/open/close/len and then higher-order functions follow at the end. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | arm: semihosting: fix up compile bugsLinus Walleij2014-12-29-50/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is currently a regression when using newer ARM64 compilers for semihosting: the way long types are inferred from context is no longer the same. The semihosting runtime uses long and size_t, so use this explicitly in the semihosting code and interface, and voila: the code now works again. Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Suggested-by: Mark Hambleton <mark.hambleton@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | arm: semihosting: staticize internal functionsLinus Walleij2014-12-29-8/+9
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semihosting code exposes internal file handle handling functions to read(), open(), close() and get the length of a certain file handle. However the code using it is only interested in either reading and entire named file into memory or getting the file length of a file referred by name. No file handles are used. Thus make the file handle code internal to this file by removing these functions from the semihosting header file and staticize them. This gives us some freedom to rearrange the semihosting code without affecting the external interface. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: UniPhier: select CONFIG_SPLMasahiro Yamada2014-12-18-0/+1
| | | | | | | | | | | | Now UniPhier platform is only supported with SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada2014-12-18-4/+0
| | | | | | | | | | | | init_page_table is only set on SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: fix property names of aliases nodes of device treesMasahiro Yamada2014-12-18-15/+15
|/ | | | | | | The property name of the "aliases" node should be "serial*" to assign a desired number for the device sequence number. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-43/+78
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| * socfpga: correctly increment freeze_controller_base addressDinh Nguyen2014-12-06-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * socfpga: add missing struct member fifo_triple_byteDinh Nguyen2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | socfpga_scan_manager structure was missing a data member. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.hStefan Roese2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bitsStefan Roese2014-12-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
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