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| * | ARM: tegra: pull Tegra210 SoC DT from Linux v4.7Stephen Warren2016-09-27-80/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Brought in the correct Tegra210 CAR binding; the old file in U-Boot appears to be a renamed version of the Tegra124 bindings rather than the real Tegra210 version. * Conversion of SPI and UART nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot, including separation of the Tegra LIC (Legacy IRQ controller) and GIC. * Node sort order fixes. Remaining deltas relative to the Linux DT: * U-Boot has enabled PCIe for Tegra210, but the kernel hasn't yet. * The GPIO node compatible value in the kernel explicitly includes Tegra124 values whereas U-Boot does not. I'll send a kernel patch to correct this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pull Tegra124 SoC DT from Linux v4.7Stephen Warren2016-09-27-7/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * USB phy_type property is aligned with the kernel, so board files are updated so the final DT content doesn't change. I'm not convinved that Nyan uses HSIC phy_type. However, I'd rather this change be a no-op, and any DT bug-fixes be separate. * Sync misc changes from the kernel: missing DT content, minor compatible value fixes, typos. Remaining deltas relative to the Linux DT: * U-Boot uses #address-cells/#size-cells of 1 whereas the kernel uses 2. I believe U-Boot's DT parsing currently assumes that these values match the physical address size, so I didn't synchronize this part of the DT. * U-Boot uses the original XUSB PHY DT binding, wherease the kernel DT has moved to a newer version. Thus, XUSB client nodes include properties names phys and phy-names that do not appear in the kernel, and don't include pad definitions in the padctl node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pull Tegra114 SoC DT from Linux v4.7Stephen Warren2016-09-27-129/+627
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra114-mc.h since tegra114.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * USB node compatible values in U-Boot explicitly list Tegra114 values whereas the kernel does not. I'll send a kernel patch to correct this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pull Tegra30 SoC DT from Linux v4.7Stephen Warren2016-09-27-143/+758
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Modification of PCIe memory region addresses. The HW memory layout is programmable, so this should work fine, and Beaver PCIe was tested without issue. * Removal of pcie_xclk from the PCIe node and clock binding header. This clock doesn't exist and isn't used; only a reset with this ID exists. * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Changed the phy_type value for the second USB port. This required board DTs to be updated to keep the same configuration. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra30-mc.h since tegra30.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * None. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pull Tegra20 SoC DT from Linux v4.7Stephen Warren2016-09-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This brings in a few minor fixes since the last sync. The largest change is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock doesn't actually exist. Remaining deltas: * Addition of u-boot,dm-pre-reloc property to a couple of nodes. * Addition of the NAND controller, which Linux doesn't yet support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: remove "0, " from DT unit addressesStephen Warren2016-09-27-82/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently the unit address in a DT node name is now supposed to be a single integer value, rather than a comma-separated list of individual cell values. Fix the U-Boot DTs to comply with this naming convention. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: Add DM_MMC support to Tegra MMC driverTom Warren2016-09-27-35/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (swarren, fixed some NULL pointer dereferences, removed extraneous changes, rebased on various other changes, removed non-DM support etc.) Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: set MMC pin mux in board_init()Stephen Warren2016-09-27-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Most other pin mux is configured in this function. This removes the need to do it in an MMC-specific initialization function, which is good since that function is going away later in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: priv struct and naming cleanupStephen Warren2016-09-27-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct mmc_host is a Tegra-specific structure, but the name implies it's something defined by core MMC code, which is confusing. Rename it to struct tegra_mmc_priv to make its purpose more obvious. The new name is also more appropriate for a DM driver private data structure, which will be relevant later in this series. Nothing needs access to this type except the MMC driver itself. Move the definition into the driver C file. Make sure all Tegra MMC functions are named tegra_mmc_*. Even though they're all static, it's useful to have good naming so that symbol tables are easy to interpret. A few functions aren't renamed by this patch since they'll be deleted by a subsequent patch in this series. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: move pad_init_mmc() into MMC driverStephen Warren2016-09-27-36/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pad_init_mmc() is performing an SoC-specific operation, using registers within the MMC controller. There's no reason to implement this code outside the MMC driver, so move it inside the driver. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: use correct alias for SDHCI/MMC nodesStephen Warren2016-09-27-48/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra MMC driver currently honors "sdhci" entries in /aliases. The MMC core however uses "mmc" entries in /aliases. This difference will be relevant once the Tegra MMC driver is converted to DM, and the MMC core handles alias lookups. To avoid issues during that conversion, fix the Tegra MMC driver and all Tegra DTs to use the same alias name as the MMC core does. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fdt: Add 'non-removable' property to all eMMC nodesTom Warren2016-09-27-0/+13
| |/ | | | | | | | | | | | | | | | | | | | | During debug of the DM_MMC changes to the Tegra MMC driver, I noticed that the 'removable' property wasn't being set correctly for the eMMC parts on most Tegra boards. Since the kernel DTS has this property set correctly, it should be in U-Boot's Tegra DT too. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm64: mvebu: armada-7040-db.dts: Add I2C and SPI aliasesStefan Roese2016-09-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C and SPI aliases to enable usage in U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Armada 7K/8K: Add COMPHY device tree nodesStefan Roese2016-09-27-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the COMPHY device tree nodes that are still missing to the Armada 7K/8K dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: armada-ap806.dtsi: Add clock-frequency to UART DT nodeStefan Roese2016-09-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock frequency needs to be provided in the DT. Otherwise the driver won't start in U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add Armada 7K db-88f7040 development board supportStefan Roese2016-09-27-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell Armada 7K DB-88F7040 development board. Supported are the following interfaces: - UART - SPI (incl. SPI NOR) - I2C - USB - SATA / AHCI Support for other interfaces will follow. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add basic support for the Marvell Armada 7K/8K SoCStefan Roese2016-09-27-110/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compared to the Armada 3700, the Armada 7K and 8K are much more on the high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as opposed to the Cortex-A53 for the Armada 3700. The Armada 7K and 8K also use a fairly unique architecture, internally they are composed of several components: - One AP (Application Processor), which contains the processor itself and a few core hardware blocks. The AP used in the Armada 7K and 8K is called AP806, and is available in two configurations: dual Cortex-A72 and quad Cortex-A72. - One or two CP (Communication Processor), which contain most of the I/O interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP, while the 8K family chips integrate two CPs, providing two times the number of I/O interfaces available in the CP. The CP used in the 7K and 8K is called CP110. All in all, this gives the following combinations: - Armada 7020, which is a dual Cortex-A72 with one CP - Armada 7040, which is a quad Cortex-A72 with one CP - Armada 8020, which is a dual Cortex-A72 with two CPs - Armada 8040, which is a quad Cortex-A72 with two CPs This patch adds basic support for this ARMv8 based SoC into U-Boot. Future patches will integrate other device drivers and board support, starting with the Marvell DB-88F7040 development board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Armada 7K/8K: Add Armada 7K/8K dts filesStefan Roese2016-09-27-0/+743
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch integrates the Armada 7K/8K dts files from the latest submission on the linux-arm-kernel mailing list. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add Armada 3700 db-88f3720 development board supportStefan Roese2016-09-27-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell Armada 3700 DB-88F3720 development board. Supported are the following interfaces: - UART - SPI (incl. SPI NOR) - I2C - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* | arm64: mvebu: Add support for the Marvell Armada 3700 SoCStefan Roese2016-09-27-12/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 3700 integrates the following interfaces (not complete list): - Dual Cortex-A53 ARMv8 - USB 3.0 - SATA 3.0 - PCIe 2.0 - 2 x Gigabit Ethernet 1Gbps / 2.5Gbps - ... This patch adds basic support for this ARMv8 based SoC into U-Boot. Future patches will integrate other device drivers and board support for the Marvell DB-88F3720 development board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* | arm64: mvebu: Armada 3700: Add USB device tree nodesStefan Roese2016-09-27-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the USB device tree nodes that are still missing to the Armada 3700 dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* | arm64: mvebu: Armada 3700: Add COMPHY device tree nodesStefan Roese2016-09-27-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the COMPHY device tree nodes that are still missing to the Armada 3700 dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* | arm64: mvebu: Armada 3700: Add I2C device tree nodesStefan Roese2016-09-27-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the I2C device tree nodes that are still missing to the Armada 3700 dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* | arm64: mvebu: Armada 3700: Add ethernet device tree nodesStefan Roese2016-09-27-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ethernet device tree nodes that are still missing to the Armada 3700 dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* | arm64: mvebu: Armada 3700: Add SPI device tree nodesStefan Roese2016-09-27-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SPI device tree nodes that are still missing to the Armada 3700 dts files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | arm64: mvebu: Armada 3700: Add Armada 37xx dts filesStefan Roese2016-09-27-0/+339
|/ | | | | | | | | | | | | | | This patch integrates the Armada 3700 dts files from the latest submission on the linux-arm-kernel mailing list. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-40/+1019
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv7: ls102xa: Rename GIC_ADDR and DCSR_RCPM_ADDRYork Sun2016-09-26-4/+4
| | | | | | | | | | | | | | | | | | Instead of using CONFIG_* name space, rename these two macros to SYS_FSL_* space. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv7: ls1021a: Convert CONFIG_LS1_DEEP_SLEEP to Kconfig optionYork Sun2016-09-26-0/+5
| | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig optionYork Sun2016-09-26-2/+17
| | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
| * armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021AYork Sun2016-09-26-8/+16
| | | | | | | | | | | | | | | | | | Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun2016-09-26-4/+11
| | | | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-14-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046ardb: Add LS1046ARDB board supportMingkai Hu2016-09-14-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: disable SATA ECC in DCSRShaohui Xie2016-09-14-0/+4
| | | | | | | | | | | | | | | | | | This is a workaround to fix SATA CRC error. Once the root cause is found the ECC disabling will be removed. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable DDR erratum for ls1046aShengzhou Liu2016-09-14-0/+6
| | | | | | | | | | | | | | | | | | Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: spl: remove BSS clearing and board_init_rQianyu Gong2016-09-14-5/+0
| | | | | | | | | | | | | | | | | | | | As per the top level U-Boot README "Board Initialisation Flow" section, board_init_f() should return without calling board_init_r() directly. Clearing BSS and calling board_init_r() will be done in crt0_64.S. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone appShaohui Xie2016-09-14-0/+2
| | | | | | | | | | | | | | | | The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latencyMingkai Hu2016-09-14-0/+15
| | | | | | | | | | | | | | | | | | | | | | According to design specification, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, so increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-14-1/+248
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add EPU Finite State MachineHongbo Zhang2016-09-14-0/+165
| | | | | | | | | | | | | | | | The EPU Finite State Machie (FSM) is used in both the last stage of system suspend and the earliest stage of system resume. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add registers definition for system sleepHongbo Zhang2016-09-14-1/+53
| | | | | | | | | | | | | | | | This patch adds definitions of all the regesters necessary for system sleep. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: psci: make v7_flush_dcache_all public for all psci codeHongbo Zhang2016-09-14-3/+5
| | | | | | | | | | | | | | | | | | | | | | The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-14/+0
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+41
| | | | | | | | | | | | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-14-4/+10
| | | | | | | | | | | | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang2016-09-14-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-08-24 19:19:26 +0000