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* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-01-27-64/+109
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| * ARM64: zynqmp: Add support for SD1 boot modeMichal Simek2016-01-27-1/+2
| | | | | | | | | | | | | | SD1 boot mode is using different bootmode values. Add support for this mode used on DC1. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Modify the SD and QSPI bootmode valuesSiva Durga Prasad Paladugu2016-01-27-0/+3
| | | | | | | | | | | | | | | | Modify the SD bootmode value to 0x3 as per latest spec. Also add new boot mode QSPI 32 bit boot mode Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: DT: Fix UART compatible stringSoren Brinkmann2016-01-27-2/+2
| | | | | | | | | | | | | | ZynqMP has r1p12 not r1p8. r1p12 contains break detection support. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Correct the watchdog timer interrupt numberPunnaiah Choudary Kalluri2016-01-27-1/+1
| | | | | | | | | | | | | | | | Corrected the watchdog timer interrupt number. Origin value was for CSUPMU watchdog. Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Fix coding style in phy nodeMichal Simek2016-01-27-1/+1
| | | | | | | | | | | | | | Trivial fix. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Add initial support for the first siliconMichal Simek2016-01-27-2/+6
| | | | | | | | | | | | Add basic configuration for the first silicon. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Use the same U-Boot version with/without ATFMichal Simek2016-01-27-8/+51
| | | | | | | | | | | | | | | | Remove SECURE_IOU option which is not needed. U-Boot itself can detect which EL level it is on and based on that use do platform setup. It also simplify usage because one Kconfig entry is gone. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Move spi node to aligned locationMichal Simek2016-01-27-27/+27
| | | | | | | | | | | | | | Keep nodes aligned. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Fix all remaining zynq platform to use stdout-pathMichal Simek2016-01-27-12/+8
| | | | | | | | | | | | Fix console setup for all remaining zynq boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Clean DTSI coding styleMichal Simek2016-01-27-5/+5
| | | | | | | | | | | | | | | | | | Fix minor indentation problems. Signed-off-by: Michal Simek <monstr@monstr.eu> Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Do not select options if SPL is not enabledMichal Simek2016-01-27-3/+3
| | | | | | | | | | | | | | Zynq setups some default options for SPL but not all targets are enabling SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Remove memory division by 2 for ECC caseMichal Simek2016-01-27-2/+0
| | | | | | | | | | | | | | | | | | For ECC case u-boot divided memory by 2 because one u-boot could be used for both cases when ECC is off or on. Remove this division and make sure that dts file contain the correct memory size when ECC is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm: mvebu: Add support for the Armada XP theadorable boardStefan Roese2016-01-27-1/+151
|/ | | | | | | | | | | | | | | | | | | This patch adds support for the Armada XP (MV78260) based theadorable board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR, LCD and SATA (SSD) interfaces / devices. Two defconfigs are added: theadorable_defconfig: The production U-Boot version with a stripped down drivers and feature list. This removes networking, USB and PCI support. theadorable_debug_defconfig: The debugging / testing U-Boot version with full support for all drivers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-01-26-19/+186
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| * sunxi: Add suport for A83T based Banana-pi M3 BoardVishnu Patekar2016-01-26-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | Add dts and defconfig for Banana-pi M3 board. It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI, mic, AP6212 Wifi, etc on it. It is paired with AXP813 PMIC which is almost same as AXP818. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com: rename to Sinovoip_BPI_M3_defconfig/sun8i-a83t-sinovoip-bpi-m3.dts] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add support for LPDDR3 for A83TVishnu Patekar2016-01-26-5/+54
| | | | | | | | | | | | | | | | | | Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T. Mostly the timing parameters are different from DDR3. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Groundwork to support new dram type for A83TVishnu Patekar2016-01-26-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, Allwinner Homlet v1.2 has DDR3. This adds groundwork to support for new DRAM type for A83T. Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must be set in respective board defconfig. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Redundant code cleanup from a83t dram initVishnu Patekar2016-01-26-5/+0
| | | | | | | | | | | | | | | | This removes the redundant lines of code from mctl_sys_init. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Support PSCI ops on Allwinner H3Chen-Yu Tsai2016-01-26-2/+2
| | | | | | | | | | | | | | | | | | H3 has the same power sequencing procedure as the A31/A31s, which includes the power clamps. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Support H3 CCU security switchesChen-Yu Tsai2016-01-26-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H3's CCU includes some switches which disable non-secure access to some of the more critical clock controls, such as MBUS, PLLs, and main platform busses. Configure them to enable non-secure access. For now the only SoC that has this feature is the H3. For other platforms just use a default (weak) empty function so things do not break. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3Chen-Yu Tsai2016-01-26-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Memory Touch Arbiter is the same thing as the TrustZone Protection Controller found on A31/A31s. Access to many peripherals on the H3 can be controlled by the SMTA, and the settings default to secure access only. This patch supports the new settings, and sets them to allow non-secure access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-01-26-0/+14
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| * video: Add support for Armada XP LCD controllerStefan Roese2016-01-23-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the LCD controller of the Marvell Armada XP SoC. An AXP based custom board port will be added later, to use this driver to display a splash screen via the bmp command later. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> [agust: rebased] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2016-01-25-10/+188
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| * | imx: mx7: default enable MDIO open drainPeng Fan2016-01-24-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ul/sx: fix mmdc_ch0 clk calculationPeng Fan2016-01-24-4/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: add more entry for mxc_ccm_regPeng Fan2016-01-24-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | Add more entries for structure mxc_ccm_reg. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: nand: update GPMI NAND driver to support MX7Peng Fan2016-01-24-2/+2
| | | | | | | | | | | | | | | | | | | | | Update GPMI NAND driver and BCH head file to support i.MX7 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: apbh_dma: Update APBH-DMA for MX7DPeng Fan2016-01-24-4/+4
| |/ | | | | | | | | | | | | Update APBH-DMA driver and head files to support i.MX7D Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | bug.h: move BUILD_BUG_* defines to include/linux/bug.hMasahiro Yamada2016-01-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_BUG_* macros have been defined in several headers. It would be nice to collect them in include/linux/bug.h like Linux. This commit is cherry-picking useful macros from include/linux/bug.h of Linux 4.4. I did not import BUILD_BUG_ON_MSG() because it would not work if it is used with include/common.h in U-Boot. I'd like to postpone it until the root cause (the "error()" macro in include/common.h causes the name conflict with "__attribute__((error()))") is fixed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm, powerpc: Update cc-version tests to check for cc-name as wellTom Rini2016-01-25-1/+2
|/ | | | | | | | For compatibility clang will report some gcc version. However since we are checking gcc versions in order to then fail to build, we should limit these tests only to when we are using gcc and not clang. Signed-off-by: Tom Rini <trini@konsulko.com>
* rockchip: Add support for Raxda Rock 2Simon Glass2016-01-21-0/+13
| | | | | | | | | | | | This board includes an RK3288 SoC on a SOM. It can be mounted on a base-board which provides a wide range of peripherals. So far this is verified to boot to a prompt from a microSD card. The serial console works as well as HDMI. Thanks to Tom Cubie for sending me a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rock2: dts: Make changes for U-BootSimon Glass2016-01-21-0/+21
| | | | | | Add the required pre-relocation tags and SDRAM init information for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rock2: Bring in device tree files from LinuxSimon Glass2016-01-21-0/+458
| | | | | | | Bring in the current device tree files for rock2 from linux/next commit 719d6c1. Hopefully this is the latest one. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: dts: Sync up SPDIF node with LinuxSimon Glass2016-01-21-0/+21
| | | | | | | This has been added and we have references to it in the rock2 board. Add this node. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Enable EDP and HDMI video outputSimon Glass2016-01-21-0/+6
| | | | | | | | | | | Enable these devices using the VOPL video output device. We explicitly disable VOPB in the device tree to avoid it taking over. Since this device has an LCD display this comes up by default. If the display fails for some reason then it will attempt to use HDMI. It is possible to force it to fail (and thus fall back to HDMI) by puting 'return -EPERM' at the top of rk_edp_probe(). For now there is no easy way to select between the two. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+64
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Fix the SDRAM timingSimon Glass2016-01-21-1/+1
| | | | | | | There is a minor error in the SDRAM timing. It does not seem to affect anything so far. Fix it just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Drop MMC support code when not neededSimon Glass2016-01-21-2/+4
| | | | | | When the board does not use MMC SPL this code is a waste of space. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Tidy up the register-access macrosSimon Glass2016-01-21-3/+4
| | | | | | | | | These work reasonable well, but there are a few errors: - Brackets should be used to avoid unexpected side-effects - When setting bits, the corresponding upper 16 bits should be set also Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Use syscon_get_first_range() where possibleSimon Glass2016-01-21-14/+3
| | | | | | | This is a shortcut to obtaining a register address. Use it where possible, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Tidy up a few commentsSimon Glass2016-01-21-2/+2
| | | | | | Fix spaces in two comments in this file. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add a simple 'clock' commandSimon Glass2016-01-21-0/+24
| | | | | | Add a command that displays the PLLs and their current rate. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Don't skip low-level initSimon Glass2016-01-21-0/+8
| | | | | | | At present the low-level init is skipped on rockchip. Among other things this means that the instruction cache is left disabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a video-output driverSimon Glass2016-01-21-0/+349
| | | | | | | | Some rockchip SoCs include video output (VOP). Add a driver to support this. It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and eDP are supported. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip eDPSimon Glass2016-01-21-0/+636
| | | | | | | Some Rockchip SoCs support embedded DisplayPort output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip HDMISimon Glass2016-01-21-0/+456
| | | | | | | | | | | | Some Rockchip SoCs support HDMI output. Add a display driver for this so that these displays can be used on supported boards. Unfortunately this driver is not fully functional. It cannot reliably read EDID information over HDMI. This seems to be due to the clocks being incorrect - the I2C bus speed appears to be up to 100x slower than the clock settings indicate. The root cause may be in the clock logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Rename the CRU_MODE_CON fieldsSimon Glass2016-01-21-29/+29
| | | | | | These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org>
* pwm: rockchip: Add a PWM driver for Rockchip SoCsSimon Glass2016-01-21-0/+41
| | | | | | Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-09-18 06:16:00 +0000