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* MLK-13645 mx7ulp: Modify FDT file to disable SD3.0 for mfgtoolimx_v2016.03_4.1.30_7ulp_alphaYe Li2016-12-23-0/+38
| | | | | | | | | | Since the SD3.0 kernel driver needs M4 image support, this causes problem to mfgtool. To decouple the relationship, we modify the FDT file in u-boot to disable SD3.0 when booting for mfgtool. So the kernel won't depend on M4 image. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit 1826d6e4dc732521190c742f812193be95eea211)
* MLK-13602-1 mx6: Add i.MX6ULL fused modules checking supportYe Li2016-12-14-1/+44
| | | | | | | Add the modules disable fuses mapping with FDT nodes and devices name. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13546 mx7ulp_arm2: Add validation board supportYe Li2016-12-02-0/+9
| | | | | | | | | | | | | This patch addes board level codes for MX7ULP ARM2 board. Since only 14x14 ARM2 board is ready, we only support this board. 10x10 board will support in future. eMMC/SD1/UART are ready in this patch. Other modules need board rework to test. Build target: mx7ulp_14x14_arm2_config Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13545 mx7ulp: Add HAB boot supportYe Li2016-12-01-0/+21
| | | | | | | | | | Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13544 mx7ulp: Modify MX7ULP arch codes to use imx-commonYe Li2016-12-01-39/+24
| | | | | | | | This patch modifies MX7ULP arch codes to reuse some functions already in imx-common, like cache and HAB. To do this, we need to add a dummy SOC type and chip type for MX7ULP and its relevant checking. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13532 misc: ocotp: ulp: fix fuse readPeng Fan2016-11-29-0/+1
| | | | | | | There is no hole in i.MX7ULP1 OCOTP space, so the phy_index is the same one with index. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13525-1 mx7ulp: Add common plugin codes for mx7ulpYe Li2016-11-25-0/+105
| | | | | | | Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2 header. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-19 imx: mx7ulp_evk: Add EVK boards support codesYe Li2016-11-22-0/+11
| | | | | | | | | | | | | | Add basic support for i.MX7ULP EVK board. I2C, SD/eMMC, UART, QSPI and USB are added. Use target mx7ulp_evk_config to select the configuration. Use mx7ulp_evk_emmc_config for eMMC boot. Use mx7ulp_evk_m4boot_config for binding and booting m4 image in single boot mode. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-12 gpio: Add Rapid GPIO2P driver for i.MX7ULPYe Li2016-11-22-0/+22
| | | | | | | | | | | | | | Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. Have added all ports on RGPIO2P_0 and RGPIO2P_1. The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set to y to enable the drivers. To use the GPIO function, the IBE and OBE needs to set in IOMUXC. We did not set the bits in driver, but leave them to IOMUXC settings of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number for gpio APIs access. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-11 mx7ulp: Implement the clock functions for i2c driverYe Li2016-11-22-0/+44
| | | | | | | Implement the i2c clock enable and get function for mx7ulp. These functions are required by imx_lpi2c driver. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-9 mx7ulp: Add lpuart DM device and clock supportYe Li2016-11-22-3/+45
| | | | | | | Add the DM device and re-implement the imx_get_uartclk according to the LPUART_BASE configuration. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-8 serial_lpuart: Add 32LE support for i.MX7ULPYe Li2016-11-22-0/+42
| | | | | | | | | | | | | Modify the lpuart to support the register access in little endian way with 32bits for i.MX7ULP. Need to enable CONFIG_LPUART_32LE_REG for the using. Also add the lpuart_fsl register structure and registers bits definitions in registers header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Teo Hall <teo.hall@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13450-7 mx7ulp: Add M4 core boot support when using single boot modeYe Li2016-11-22-0/+40
| | | | | | | | | | | | | | | | | | The single boot mode in MX7ULP will only boot up A7, the M4 is running in ROM by checking entry from SIM0 GP register. In this patch, We bind M4 image with u-boot.bin before attaching the imx header. So the whole image (included M4 image) will be loaded by A7 ROM into DDR. Then when u-boot is up, it will try to load M4 image into TCML and boot it there. Since M4 image will not be relocated in u-boot codes, we must load it during board_f. Current implementation put it in arch_cpu_init to get M4 booted as quick as possible. We requires the M4 image with IVT head and padding embedded, not a RAW binary. The image should be same as what is used for M4 QSPI boot in dual boot mode. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-6 mx7ulp: Add soc level initialization codes and functionsYe Li2016-11-22-1/+322
| | | | | | | | | | | | Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-5 mx7ulp: Add clock framework and functionsYe Li2016-11-22-1/+2391
| | | | | | | | | | | | | | | | | Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-4 mx7ulp: Add iomux pins header fileYe Li2016-11-22-0/+910
| | | | | | | | | | | | Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins to add IOMUX_CONFIG_MPORTS flags. Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address to aligin with it. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-3 mx7ulp: Add iomux driver to support IOMUXC0 and IOMUXC1Ye Li2016-11-22-0/+170
| | | | | | | | | | Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-2 mx7ulp: Add registers address header fileYe Li2016-11-22-0/+1151
| | | | | | | | Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-1 mx7ulp: Add new i.MX series mx7ulp to KconfigYe Li2016-11-22-1/+19
| | | | | | | | | Since mx7ulp is a new series which have different architecture as previous i.MX platforms. We create a new cpu folder for it. This patch addes it to Kconfig. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13499 imx6sll: add epdc splash screen supportRobby Cai2016-11-21-1/+3
| | | | | | | add splash screen feature for epdc. it's tested on imx6sll arm2 board and evk board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-13476 imx: 6sx: fix ECSPI5 basePeng Fan2016-11-17-0/+2
| | | | | | ECSPI5 redefined. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13289 imx: mx6sxscm: generic mx6sxscm board supportJuan Gutierrez2016-10-26-0/+7
| | | | | | | | | | | | | | Provide the generic support for i.MX6SX SCM boards i.MX6SX SCM board file with the generic configuration, LPDDR2 memory calibration and build support is provided. - LPDDR2 memory configuration files for 1GB and 512MB. - plugin support for the above configurations. - driver support for: uart, qspi, i2c, usb, mmc. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13255 imx: mx6dqscm: generic mx6dqscm board supportJuan Gutierrez2016-10-21-0/+6
| | | | | | | | | | | | | Provide the generic support for i.MX6DQ SCM boards - LPDDR2 memory configuration files for 1GB, 2GB and 512MB. - plugin support for the above configurations. - fix and interleave memory mode (selected by CONFIG option) - driver support for: uart, spi, i2c, usb, sata and fec. - Android support Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13352 imx: mx6sll: support mx6sllevk boardPeng Fan2016-10-19-0/+7
| | | | | | | | | | Add mx6sll evk board support. USB/LCDIF/I2C/SD/EMMC/WDOG supported. The ddr script is from mx6sll lpddr3 arm2 board. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-15 imx: mx6sll: add mx6sll arm2 supportPeng Fan2016-10-11-0/+7
| | | | | | | | | | | Add mx6sll lpddr3/lpddr2 arm2 support. LCDIF/SPI/USB/PMIC supported. LPDDR3 DDR version: 1.2 LPDDR2 DDR version: initial version. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-14 imx-common: lcdif: update lcdif regs for i.MX6SLLPeng Fan2016-10-11-4/+5
| | | | | | | Update lcdif regs for i.MX6SLL Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2016-10-11-6/+71
| | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-9 imx: mx6sll: add Kconfig entry for i.MX6SLLPeng Fan2016-10-11-0/+4
| | | | | | add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-8 imx-common: cache: configure L2 Cache for i.MX6SLLPeng Fan2016-10-11-1/+1
| | | | | | Configure L2 Cache for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2016-10-11-5/+16
| | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-6 imx: mx6sll: add clock support for i.MX6SLLPeng Fan2016-10-11-36/+158
| | | | | | | Update clock settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-5 imx: mx6sll: add iomux settingsPeng Fan2016-10-11-4/+10
| | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-4 imx-common: timer: add i.MX6SLL supportPeng Fan2016-10-11-2/+4
| | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-3 imx: mx6sll: update register addressPeng Fan2016-10-11-41/+52
| | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-2 imx: mx6sll: add pinmux header filesPeng Fan2016-10-11-0/+1021
| | | | | | Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-1 imx: Add MX6SLL CPU typePeng Fan2016-10-11-1/+4
| | | | | | | Add i.MX6SLL CPU type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* mx6: clock: Fix the logic for reading axi_alt_selFabio Estevam2016-09-18-2/+2
| | | | | | | | | | | | | | According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> (cherry picked from commit 8f2e2f15ffa1bb03b6e6e189312426059f3215d1)
* Disable MMU and Cache when using pluginUtkarsh Gupta2016-09-01-0/+28
| | | | Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
* MLK-13140 ARM: imx: update REFTOP_VBGADJ according to fuse settingBai Ping2016-08-30-5/+0
| | | | | | | | | | | | | | | | On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13124 ARM: imx: update the REFTOP_VBGADJ settingBai Ping2016-08-25-6/+32
| | | | | | | | | | | | | | | | | Per to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000' - set REFTOP_VBGADJ[2:0] to 3b'110 '110' - set REFTOP_VBGADJ[2:0] to 3b'000 '001' - set REFTOP_VBGADJ[2:0] to 3b'001 '010' - set REFTOP_VBGADJ[2:0] to 3b'010 '011' - set REFTOP_VBGADJ[2:0] to 3b'011 '100' - set REFTOP_VBGADJ[2:0] to 3b'100 '101' - set REFTOP_VBGADJ[2:0] to 3b'101 '111' - set REFTOP_VBGADJ[2:0] to 3b'111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-12929 imx6ull: support splash screen for epdcRobby Cai2016-07-29-0/+56
| | | | | | | add splash screen feature for epdc. it's tested on imx6ull arm2 board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-12964 imx: enlarge mux width to 4Peng Fan2016-07-22-8/+7
| | | | | | For i.MX6, the mux width is 4, not 3. So enlarge the width. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12988 imx: mx6ull Add board support for i.MX6ULL EVKYe Li2016-07-19-0/+13
| | | | | | | | | | | | | | | | | | | | | Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok to work. The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when it is needed. The DDR3 script is using version 1.2: File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc Test: 3 boards passed memtester. Build target: mx6ull_14x14_evk_defconfig Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12985 imx: mx6sx: Disable ENET clock before switching clock parentYe.Li2016-07-15-0/+5
| | | | | | | Need to gate ENET clock when switching to a new clock parent, because the mux is not glitchless. Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-12894 imx6ull: adjust the ldo 1.2v bandgap voltage on i.mx6ullBai Ping2016-06-08-0/+7
| | | | | | | | Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-12798 imx6ull: fix snvs tamper pin usagePeng Fan2016-05-16-16/+28
| | | | | | | | | | | | | SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable using these pins. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: iomux-v3: fix UART input selectsStefan Agner2016-05-10-4/+4
| | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2. From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12767 imx6ull: fix runtime checking for i.MX6ULLPeng Fan2016-05-09-24/+34
| | | | | | | Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12693-2 nand: mxs: correct bitflip for erased NAND pagePeng Fan2016-05-07-1/+5
| | | | | | | | | | | | | | | | | | This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx7d: fix ahb clock mux 1Stefan Agner2016-05-06-1/+1
| | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
generated by cgit v1.1 at 2025-04-23 12:35:47 +0000