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* exynos: dts: Correct EC interrupt GPIOSimon Glass2014-05-28-2/+2
| | | | | | | | Now that the GPIO numbering series has been applied, we can use the correct GPIO for the EC interrupt. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: dts: exnyos: enable dw-mmc controllerJaehoon Chung2014-05-16-1/+5
| | | | | | | | | Enabled the dw-mmc controller. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMCJaehoon Chung2014-05-16-4/+4
| | | | | | | | Exynos serise can be supported the dw-mmc controller. So, it's good that used the general prefix as "_EXYNOS_DWMMC". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: exynos: clock: modify the set_mmc_clk for exynos4Jaehoon Chung2014-05-16-5/+16
| | | | | | | | | | | | Modified the mmc_set_clock for eynos4. The goal of this patch is that fsys-div register should be reset. And retore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* board: trats2: Enable device tree on Trats2Beomho Seo2014-05-16-0/+16
| | | | | | | | | | | | This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: clock: Remove exynos4x12_set_mmc_clk functionBeomho Seo2014-05-16-28/+1
| | | | | | | | | | | | | exynos4x12_set_mmc_clk function have been removed. Because, exynos4x12_clock and exynos4_clock return same div_fsys* value. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: pinmux: add sdmmc4 gpio configratuionBeomho Seo2014-05-16-6/+29
| | | | | | | | | | | | For use dwmmc controller at exynos4, add SDMMC4 gpio configuration. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-15-9/+74
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| * ARM: tegra: use a CPU freq that all SKUs can supportStephen Warren2014-05-13-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot on Tegra30 currently selects a main CPU frequency that cannot be supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values on some others. This can result in unreliable operation of the main CPUs. Resolve this by switching to a CPU frequency that can be supported by any SKU. According to the following link, the maximum supported CPU frequency of the slowest Tegra30 SKU is 600MHz: repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary branch l4t/l4t-r16-r2 path arch/arm/mach-tegra/tegra3_dvfs.c table cpu_dvfs_table[] According to that same table, the minimum VDD_CPU required to operate at that frequency across all SKUs is 1.007V. Given the adjustment resolution of the TPS65911 PMIC that's used on all Tegra30-based boards we support, we'll end up using 1.0125V instead. At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates that VDD_CORE must be at least 1.2V on all SKUs. According to tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree), that voltage is safe for all SKUs. An alternative would be to port much of the code from tegra3_dvfs.c and tegra3_speedo.c in the kernel tree mentioned above. That's more work than I want to take on right now. While all the currently supported boards use the same regulator chip for VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we add some small conditional code to select how VDD_CORE is programmed. If this becomes more complex in the future as new boards are added, or we end up adding code to detect the SoC SKU and dynamically determine the allowed frequency and required voltages, we should probably make this a runtime call into a function provided by the board file and/or relevant PMIC driver. Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Marcel Ziswiler <marcel@ziswiler.com> Cc: Bard Liao <bardliao@realtek.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: add function to enable input clamping on tristateStephen Warren2014-05-13-0/+21
| | | | | | | | | | | | | | | | | | The HW-defined procedure for booting Tegra requires that CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux. Add a function to the pinmux driver to allow boards to do this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: add GPIO initialization table functionStephen Warren2014-05-13-0/+20
| | | | | | | | | | | | | | | | | | | | | | The HW-defined procedure for booting Tegra requires that some pins be set up as GPIOs immediately at boot in order to avoid glitches on those pins, when the pinmux is programmed. Add a feature to the GPIO driver which executes a GPIO configuration table. Board files will use this to implement the correct HW initialization procedure. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: allow pinmux mux option not to be set by init tablesStephen Warren2014-05-13-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change the mux option in HW. For pins that will be used as GPIOs, the mux option is irrelevant, so we simply don't want to define any mux option in the pinmux initialization table. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: fix CPU VDD comment in Tegra30 CPU init codeStephen Warren2014-05-13-1/+1
| | | | | | | | | | | | | | | | | | The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment implies. Fix the comment. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: set CONFIG_SYS_MMC_MAX_DEVICEStephen Warren2014-05-13-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_API is ever to be enabled on Tegra, this define must be set, since api/api_storage.c uses it. A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE 1) It isn't documented in README. The same is true for a lot of similar defines used by api_storage.c. 2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the valid values are 0..n-1 not 0..n. However, I this patch does not address those shortcomings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-15-689/+2616
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| * | S5P: Exynos: Add GPIO pin numbering and rename definitionsAkshay Saraswat2014-05-13-689/+2616
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes following changes : * Adds gpio pin numbering support for EXYNOS SOCs. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. * Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation. * Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number. Example: SMDK5420 # gpio set gpa00 Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | arm: move exception handling out of start.S filesAlbert ARIBAUD2014-05-15-2426/+313
| | | | | | | | | | | | | | | | | | | | | | | | Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | arm: remove unused _end_vect and _vectors_end symbolsAlbert ARIBAUD2014-05-15-11/+0
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | arm: pxa: move SP check from start.S to cpuinfo.cAlbert ARIBAUD2014-05-15-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | PXA start.S has a PXA (variant) specific check in start.S. Move it to cpuinfo.c. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marex@denx.de>
* | | arm: move reset_cpu from start.S into cpu.cAlbert ARIBAUD2014-05-15-33/+27
| | | | | | | | | | | | | | | | | | | | | | | | CPUs arm946es and sa1100 both define the reset_cpu() function in their start.S file. Move this cpu-specific code into cpu.c so that start.S only contains ARM generic code. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | arm1136: move cache code from start.S to cache.cAlbert ARIBAUD2014-05-15-13/+10
| |/ |/| | | | | | | | | | | arch/arm/cpu/arm1136/start.S contain a cache flushing function. Remove the function and move its code into arch/arm/lib/cache.c. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge branch 'u-boot/master'Albert ARIBAUD2014-05-09-82/+155
|\ \ | |/ |/| | | | | | | | | Conflicts: drivers/net/Makefile (trivial merge)
| * usb: ehci: rmobile: Add support ehci host driver of rmobile SoCsNobuhiro Iwamatsu2014-04-30-0/+147
| | | | | | | | | | | | | | | | The rmobile SoC has usb host controller. This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * ARM:tegra20: Remove aes debug printsTom Rini2014-04-18-9/+0
| | | | | | | | | | | | | | | | In 6e7b9f4 some of the debug prints for AES code moved into the generic code, so we remove these additional calls. Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Tom Warren <twarren@nvidia.com>
| * aes: make apply_cbc_chain_data non-staticStephen Warren2014-04-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart code. This function was recently moved into the core aes.c and made static, which prevents the Tegra code from compiling. Make it public again to avoid the compile errors: arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’: arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration] arch/arm/cpu/built-in.o: In function `sign_object': .../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data' .../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data' Fixes: 6e7b9f4fa0ae ("aes: Move the AES-128-CBC encryption function to common code") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
| * kbuild: use boolean macros to select tegra*-common directoryMasahiro Yamada2014-04-17-1/+4
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * Merge branch 'next'Tom Rini2014-04-17-70/+2
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| | * aes: Move the AES-128-CBC encryption function to common codeMarek Vasut2014-03-21-70/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the AES-128-CBC encryption function implemented in tegra20-common/crypto.c into lib/aes.c . This is well re-usable common code. Moreover, clean the code up a bit and fix the kerneldoc-style annotations. Signed-off-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-21-255/+3050
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| * | | arm, da850: staticize funtionsManish Badarkhe2014-04-17-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make funtions static which are locally used in file and remove the declaration from header file. Signed-off-by: Manish Badarkhe <badarkhe.manish@gmail.com>
| * | | am335x: Switch to CONFIG_SKIP_LOWLEVEL_INIT from guarding SPL or NOR_BOOTTom Rini2014-04-17-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of SPL or NOR_BOOT (no SPL involved) we need to include certain code in the build. Use !CONFIG_SKIP_LOWLEVEL_INIT rather than CONFIG_SPL_BUILD || CONFIG_NOR_BOOT to make the code clearer, and to make supporting XIP QSPI boot clearer in the code. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Wolfgang Denk <wd@denx.de>
| * | | keystone2: net: add keystone ethernet driverKaricheri, Muralidharan2014-04-17-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ethernet driver configures the CPSW, SGMI and Phy and uses the the Navigator APIs. The driver supports 4 Ethernet ports and can work with only one port at a time. Port configurations are defined in board.c. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
| * | | keystone2: add keystone multicore navigator driverVitaly Andrianov2014-04-17-0/+570
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multicore navigator consists of Network Coprocessor (NetCP) and Queue Manager sub system. More details on the hardware can be obtained from the following links:- Network Coprocessor: http://www.ti.com/lit/pdf/sprugz6 Multicore Navigator: http://www.ti.com/lit/pdf/sprugr9 Multicore navigator driver implements APIs to configure the Queue Manager and NetCP Pkt DMA. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | | k2hk: add support for k2hk SOC and EVMVitaly Andrianov2014-04-17-0/+1912
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
| * | | i2c, davinci: convert driver to new mutlibus/mutliadapter frameworkVitaly Andrianov2014-04-17-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add davinci driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | | i2c, davinci: move i2c_defs.h to the drivers/i2c directoryKaricheri, Muralidharan2014-04-17-68/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the davinci i2c_defs.h file to drivers.i2c directory. It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs. Not used "git mv" command to move the file because small part of it with definitions specific for Davinci SOCs has to remain in the arch/arm/include/asm/arch-davinci. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | | arm: add support for arch timerVitaly Andrianov2014-04-17-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add basic support for the architecture timer found on recent ARMv7 based SoCs. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
| * | | dra7xx_evm: Add QSPI_4 support, qspiboot build targetTom Rini2014-04-17-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad) read support as well. This means we can be given one of two boot device values, but don't care which it is, so perform a fixup on the QSPI_4 value. We add a qspiboot build target to better show how you would use QSPI as a boot device in deployment. When we boot from QSPI, we can check the environment for 'boot_os' to control Falcon Mode. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | | OMAP3: beagle-xm: generate fake USB ethernet MAC address from dieidNishanth Menon2014-04-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to OMAP5uEVM, PandaBoard, BeagleBoard-XM has a USB based ethernet without MAC address embedded. So fake a MAC address following the similar strategy used on OMAP5 and PandaBoard family. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | | omap3/sys_info: provide interface to read die idNishanth Menon2014-04-17-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | introduce get_die_id() function which allows generation of information such as fake MAC address from the processor ID code. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | | OMAP: common: consolidate fake USB ethernet MAC address creationNishanth Menon2014-04-17-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI platforms such as OMAP5uevm, PandaBoard, use equivalent logic to generate fake USB MAC address from device unique DIE ID. Consolidate this to a generic location such that other TI platforms such as BeagleBoard-XM can also use the same. NOTE: at this point in time, I dont yet see a need for a generic dummy ethernet MAC address creation function, but if there is a need in the future, this can be further abstracted out. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | | ARM: OMAP: replace custom sr32() by standard I/O accessorsWolfgang Denk2014-04-17-163/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the custom bit manipulation function sr32() by standard I/O accessors. A major motivation for this cleanup was the fact, that a number of calls of that function resulted in 32 bit wide shift operations on u32 data, which according to the C-ISO/IEC-9899-Standard provokes undefined behaviour: 6.5.7 Bitwise shift operators ... If the value of the right operand is negative or is greater than or equal to the width of the promoted left operand, the behavior is undefined. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | ARM: OMAP: hide custom bit manipulation function sr32()Wolfgang Denk2014-04-17-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only remaining user of the custom bit manipulation function sr32() is arch/arm/cpu/armv7/omap3/clock.c, so make it a static function in that file to prepare complete removal. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | ARM: OMAP: remove sr32() from OMAP board codeWolfgang Denk2014-04-17-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the custom sr32() bit manipulation function in arch/arm/cpu/armv7/omap3/board.c and board/ti/panda/panda.c by standard I/O accessors. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | ARM: tegra: pack pinmux data tables tighterStephen Warren2014-04-17-41/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use smaller fields in the Tegra pinmux structures in order to pack the data tables into a smaller space. This saves around 1-3KB for the SPL and around 3-8KB for the main build of U-Boot, depending on the board, which SoC it uses, and how many pinmux table entries there are. In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the values of PMUX_FUNC_RSVD* to values which require 16 bits to store them, but instead let their values be assigned automatically, so they end up fitting into 8 bits. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | usb: tegra: combine header fileStefan Agner2014-04-17-753/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | usb: tegra: fix PHY configurationStefan Agner2014-04-17-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: add Jetson TK1 boardStephen Warren2014-04-17-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of its design with Venice2. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: Tegra124 pinmux cleanupStephen Warren2014-04-17-577/+539
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra124_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. There are differences in the set of drive groups. I have validated this against the TRM. There are differences order of pin definitions in pinmux.c; these previously had significant mismatches with the correct order:-( I adjusted a few entries in pinmux-config-venice2.h since the set of legal functions for some pins was updated to match the TRM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: Tegra114 pinmux cleanupStephen Warren2014-04-17-573/+500
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra114_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted a few entries in pinmux-config-dalmore.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-08-27 03:22:51 +0000