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* bootstage: Replace show_boot_progress/error() with bootstage_...()Simon Glass2012-03-18-1/+1
| | | | | | | These calls should not be made directly any more, since bootstage will call the show_boot_...() functions as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Make use of BOOTSTAGE_ID_RUN_OS in show_boot_progress()Simon Glass2012-03-18-1/+1
| | | | | | | | | This changes the number 15 as used in boot_stage_progress() to use the new name provided for it. This is a separate patch because it touches so many files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* ATMEL: remove old atmel_mci driverSven Schnelle2012-03-13-1/+1
| | | | | | | | All boards are using the gen_atmel_mci driver now, so no need to carry the old driver around. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Stop using builtin_run_command()Simon Glass2012-03-06-6/+1
| | | | | | | | | | Boards can select either the 'built-in' parser or the hush parser. We should not call builtin_run_command() if we are using the hush parser. We use run_command() instead, since it knows how to call the correct parser. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Rename run_command() to builtin_run_command()Simon Glass2012-03-06-1/+1
| | | | | | | | | The current run_command() is only one of the parsing options - the other is hush. We should not call run_command() when the hush parser is being used. So we rename this function to better explain its purpose. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Remove execute permissions from source filesThomas Weber2012-03-04-0/+0
| | | | Signed-off-by: Thomas Weber <weber@corscience.de>
* armv7: omap3: leave outer cache enabledAneesh V2012-02-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Mainline kernel for OMAP3 doesn't enable L2 cache It expects L2$ to be enabled by ROM-code/bootloader. Leaving L2$ enabled can be troublesome in cases where the L2 cache is not under CP15 control, such as in Cortex-A9. This problem is explained in detail in the commit dc7100f4080952798413fb63bb4134b22c57623a However, this problem doesn't apply to Cortex-A8 because L2$ in Cortex-A8 is under CP15 control and hence the generic armv7 maintenance opertions work for it. As such we can make an exception for OMAP3 and leave the L2$ enabled when we jump to kernel. This is done by removing the strongly-linked implementation of v7_outer_cache_disable() and allowing it to fall back to the weakly linked implementation that doesn't do anything. Signed-off-by: Aneesh V <aneesh@ti.com>
* tt01: add video supportHelmut Raiger2012-02-27-0/+1
| | | | | | | | The video setup for the Epson display is provided. Addtionally some extra info is displayed next to the Linux logo. Make get_cpu_rev() publicly available (added to sys_proto.h). Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
* net: fec_mxc: add 1000 Mbps selectionTroy Kisky2012-02-27-0/+1
| | | | | | | | Define FEC_QUIRK_ENET_MAC and add to arch-mx6/imx-regs.h Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* dm6467Tevm: Use a common configuration file for davinci_dm6467evm and ↵prabhakar.csengg@gmail.com2012-02-27-1/+1
| | | | | | | | | | | | | | | | | | | | davinci_dm6467Tevm In commit 2d575e46859dd9127a9cec731ace77523e6ea2ab a separate header file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h. The substantial difference between the davinci_dm6467evm and the davinci_dm6467Tevm configuration is a single bit in the hardware revision that is passed to the Linux kernel and davinci_dm6467evm has REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a REFCLK_FREQ = 33000000. This patch removes include/configs/davinci_dm6467Tevm.h. Instead the include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined in boards.cfg. Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com> Cc: Tom Rini <trini@ti.com>
* am33xx: ddr_defs.h: Change DDR timingsChase Maupin2012-02-27-1/+1
| | | | | | | | * For cold silicon the DDR timings need to be relaxed in order for the device to boot with DDR at 266MHz * Fix proposed by James Doublesin Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
* davinci: cleanup davinci_sync_env_enetaddr() fucntionHadli, Manjunath2012-02-27-3/+6
| | | | | | | | | | | | check for the return status for eth_getenv_enetaddr_by_index() and eth_setenv_enetaddr() functions and print appropriate message on failure. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* mx35: generic: Let get_reset_cause be defined only when ↵Fabio Estevam2012-02-27-1/+1
| | | | | | | | | CONFIG_DISPLAY_CPUINFO is selected get_reset_cause() function is only used inside print_cpuinfo(), so let it be defined only when CONFIG_DISPLAY_CPUINFO is selected. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6q: Add support for ECSPI through mxc_spi driverEric Nelson2012-02-27-0/+44
| | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* mxc_spi: move machine specifics into CPU headersEric Nelson2012-02-27-0/+82
| | | | | | | | | | | | | | Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org>
* mx6q: define GPIO macros for translating between ordinals and port:indexEric Nelson2012-02-27-0/+4
| | | | | | | | | | | | | | | | | The interface to the mxc_gpio driver uses integer (ordinal) values to refer to all GPIOs on the i.MX processors. The registers themselves and much of the i.MX documentation are banked in groups of 32, and these macros allow the use of the port:index numbering for clarity. GPIO_NUMBER() converts to ordinal value from port:index GPIO_PORT() returns the port of an ordinal value GPIO_INDEX() returns the index or offset of the ordinal. Discussion on the mailing list at http://lists.denx.de/pipermail/u-boot/2012-January/116927.html Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* MX27: add missing get_tbclk()Stefano Babic2012-02-27-0/+5
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* MX28: Fix get_timer() / get_tbclk() issueMarek Vasut2012-02-27-2/+17
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* mx28: fix SPL code to make USB booting workMatthias Fuchs2012-02-27-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes booting i.MX28 CPUs via USB download. In this mode the CPU's bootrom implements a USB HID device that accepts a bootstream. When downloading the bootstream via USB, first the SPL code is received and executed. Then the u-boot image is received and called. The USB bootmode is interrupt driven. This patch fixes two things: 1) The ARM's fast interrupt mode is disabled when the SPL code has been run. So save and restore the CPSR register. 2) Save and restore c1 control register: the exception vector location needs to be set back to bootrom space to make the USB interrupts work again. The SPL code needs to change this option for the ram size probing. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* i.MX28: Fix VDDIO and VDDA setupMarek Vasut2012-02-27-4/+12
| | | | | | | | | | | | The DC power STS shouldn't be checked if booting off 5V supply. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Robert Deliën <robert@delien.nl> Cc: Fabio Estevam <festevam@gmail.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
* MX5/MX6: add missing get_ticks() and get_tbclk()Stefano Babic2012-02-27-18/+57
| | | | | | | | | | | commit f31a911fe (arm, post: add missing post_time_ms for arm) enables get_ticks and get_tbclk for all arm based boards, MX5/MX6 have not yet implemented. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Liu <jason.hui@linaro.org> CC: Marek Vasut <marek.vasut@gmail.com>
* MX31: add missing get_tbclk()Stefano Babic2012-02-27-0/+9
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Helmut Raiger <helmut.raiger@hale.at>
* MX35: add missing get_ticks() and get_tbclk()Stefano Babic2012-02-27-39/+64
| | | | | | | | commit f31a911fe (arm, post: add missing post_time_ms for arm) enables get_ticks and get_tbclk for all arm based boards, MX5/MX6 have not yet implemented. Signed-off-by: Stefano Babic <sbabic@denx.de>
* omap_hsmmc: Wait for CMDI to be clearTom Rini2012-02-15-4/+4
| | | | | | | | | | | | | | | | | Before we can send a command we need both the DATI (command inhibit on mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear. The previous behavior of only checking on DATI was insufficient on some cards and incorrect behavior in any case. This makes the code check for both bits being clear and makes the error print more clear as to what happened. DATI_CMDDIS is removed as it was unused elsewhere in the code and stood for 'DATI is set, cmds are disabled still'. Fix originally spotted by Peter Bigot. Tested-by: Peter A. Bigot <bigotp@acm.org> Tested-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
* Changes to move hawkboard to the new spl infrastructureSughosh Ganu2012-02-12-11/+26
| | | | | | | | | | | | | | | | | | This patch moves hawkboard to the new spl infrastructure from the older nand_spl one. Removed the hawkboard_nand_config build option -- The spl code now gets compiled with hawkboard_config, after building the main u-boot image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard to reflect the same. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not definedChristian Riesch2012-02-12-1/+4
| | | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGHChristian Riesch2012-02-12-1/+6
| | | | | | | | | | | | | | The V bit of the c1 register of CP15 should not be cleared on DA850 SoCs since they have no valid memory at 0x00000000. This patch introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH that allows setting the correct value for the V bit. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Reported-by: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Heiko Schocher <hs@denx.de>
* arm, arm926ejs: Flush the data cache before disabling itSughosh Ganu2012-02-12-4/+8
| | | | | | | | | | | | | | | | | | | | | The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead. Also fix the comments to match code. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Rebased and corrected commit message. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* arm, arm926ejs: Do cpu critical inits only for boards that require itChristian Riesch2012-02-12-2/+4
| | | | | | | | | | | | | | | | | This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416 "arm, arm926ejs: always do cpu critical inits" since it impacts all arm926ejs based configurations and caused problems, e.g., with the hawkboard. Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines from the board configurations that need low level initialization. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* arm, davinci: Add lowlevel_init for SoCs other than DM644XChristian Riesch2012-02-12-0/+4
| | | | | | | | | | | | | The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Tom Rini <trini@ti.com> Cc: Sergey Kubushyn <ksi@koi8.net> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* ARMV7: Fix duplicate use of "b" parameter in ACTIM_CTRLA definitionPeter Barada2012-02-12-28/+29
| | | | | | | | ACTIM_CTRLA macro errently passes "b" parameter to ACTIM_CTRLA_TRAS() instead of "c". To make usage more clear, replace all single-letter macro parameters with more descriptive parameter names. Signed-off-by: Peter Barada <peter.barada@logicpd.com>
* OMAP4460: Reduce MPU clock speed from 920 to 700Aneesh V2012-02-12-11/+11
| | | | | | | | | | We do not have thermal management or Smartreflex enabled at U-Boot level. So, it's better to stick to OPP100 for MPU instead of the OPP Turbo that is used now. Adjust the VDD_MPU accordingly. Tested-by: Sebastien Jan <s-jan@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* davinci: add support for printing clock frequencyHadli, Manjunath2012-02-12-1/+44
| | | | | | | | | add support for printing various clock frequency info found in SOC such as ARM core frequency, DSP core frequency and DDR frequency as part of bdinfo command. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com>
* davinci: remove macro CONFIG_DISPLAY_CPUINFOHadli, Manjunath2012-02-12-44/+0
| | | | | | | | | | remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer required. This is because clock info will be printed as part 'bdinfo' command and also remove support print_cpuinfo() as it will no longer be called. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com>
* omap3: fix comment typosPeter Meerwald2012-02-12-2/+2
| | | | Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
* AM3517: Changed default clock rate for AM3517Schuyler Patton2012-02-12-1/+1
| | | | | | | | | | | | AM3517: Changed default clock rate for AM3517 Changed #define MPU_M_13_ES2 from 0x1F4 to 0x258, this allows the AM3517 to boot up at 600MHz instead of 500 MHz Signed-off-by: Schuyler Patton <spatton@ti.com> CC: Tom Rini <tom.rini@gmail.com> CC: Simon Schwarz <simonschwarzcor@gmail.com> CC: Stefano Babic <sbabic@denx.de>
* OMAP4: clock-common: Move the usb dppl configuration to new funcGovindraj.R2012-02-12-21/+33
| | | | | | | | | | | usb dpll configuration is done only part of non-essential dppl configuration however if CONFIG_USB_EHCI_OMAP is defined we may have to configure usb dpll's for proper functioning of usb modules. So move the usb dppl configuration to a new func. and utilise the same during essential dpll configuration. Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* OMAP3+: Clock: Adding ehci clock enablingGovindraj.R2012-02-12-0/+30
| | | | | | | | | | Adding ehci clock enabling mechanism part of clock framework. When essential clocks are enabled during init phase usb host clocks can also be enabled from clock framework. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* ehci-omap: Clean up added ehci-omap.cGovindraj.R2012-02-12-24/+212
| | | | | | | | | | | | | | | | | | Clean up added ehci-omap.c and make it generic for re-use across omap-soc having same ehci ip block. Also pass the modes to be configured from board file and configure the ports accordingly. All usb layers are not cache aligned, till then keep cache off for usb ops as ehci will use internally dma for all usb ops. * Add a generic common header ehci-omap.h having common ip block data and reg shifts. * Rename and modify ehci-omap3 to ehci.h retain only conflicting sysc reg shifts remove others and move to common header file. * pass the board data for beagle/panda accordinly to use ehci ports. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
* ARM: EXYNOS: Add support for Exynos5 based SoCsChander Kashyap2012-02-12-12/+854
| | | | | | | | Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macroChander Kashyap2012-02-12-5/+1
| | | | | | | | | CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S5P: support generic watchdog timerMinkyu Kang2012-02-12-1/+124
| | | | | | | | This patch adds support the generic watchdog timer for s5pc1xx and exynos4 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: HeungJun, Kim <riverful.kim@samsung.com>
* ARMV7: Exynos4: Add supoort power for Exynos4HeungJun, Kim2012-02-12-0/+231
| | | | | | | | This patch adds power.h and SAMSUNG_BASE() macro for using Exynos4 power. Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARMV7: Exynos4: Add watchdog.h for Exynos4HeungJun, Kim2012-02-12-0/+53
| | | | | | | | This patch add watchdog.h for Exynos4 Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: Fix ARM Clock frequency calculationChander Kashyap2012-02-12-6/+9
| | | | | | | | | | Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calculating it as follows: ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: PWM: Add TCMPB3 field in pwm structureChander Kashyap2012-02-12-1/+1
| | | | | | | Add TCMPB3 field in pwm structure, earliar this was res1. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* bugfix: all Marvell specific build fails due to undefined reference to ↵Prafulla Wadaskar2012-02-12-0/+72
| | | | | | | | | | | | | | | | `get_ticks' after http://patchwork.ozlabs.org/patch/136415/ was applied. All Marvell build fails with below error common/libcommon.o: In function `cread_line': /home/uboot/src/u-boot-arm/common/main.c:717: undefined reference to `get_ticks' /home/uboot/src/u-boot-arm/common/main.c:717: undefined reference to `get_tbclk' /home/uboot/src/u-boot-arm/common/main.c:720: undefined reference to `get_ticks' The same is fixed for Kirkwood, ARMADA100, pantheon and orion5x SoCs Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* arm, arm-kirkwood: disable l2c before linux bootMichael Walle2012-02-12-0/+46
| | | | | | | | | | | The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Wolfgang Denk <wd@denx.de>
* orion5x: add USB host ehci-marvell supportAlbert ARIBAUD2012-02-12-0/+12
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Remove kirkwood-specifics from marvell EHCI driverAlbert ARIBAUD2012-02-12-0/+12
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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