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* arm: build arch memset/memcpy in Thumb2 modeStefan Agner2015-01-09-87/+142
| | | | | | | | | | | | | | | | | | | | | | Resynchronize memcpy/memset with kernel 3.17 and build them in Thumb2 mode (unified syntax). Those assembler files can be built and linked in ARM mode too, however when calling them from Thumb2 built code, the stack got corrupted and the copy did not succeed (the exact details have not been traced back). However, the Linux kernel builds those files in Thumb2 mode. Hence U-Boot should build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set. To build the files without warning, some assembler instructions had to be replaced with their UAL compliant variant (thanks Jeroen for this input). To build the file in Thumb2 mode the implicit-it=always option need to be set to generate Thumb2 compliant IT instructions where needed. We add this option to the general AFLAGS when building for Thumb2. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Agner <stefan@agner.ch>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-08-5/+5
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| * dt: socfpga: Replace num-chipselect with num-csMarek Vasut2015-01-07-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This optional DT property is called 'num-cs', so repair the misnomers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssiMarek Vasut2015-01-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | mx25: Fix boot hang by avoiding vector relocationFabio Estevam2015-01-08-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx25pdk hangs like this: CPU: Freescale i.MX25 rev1.2 at 399 MHz Reset cause: WDOG Board: MX25PDK I2C: ready DRAM: 64 MiB (hangs) Add a specific relocate_vectors macro that skips the vector relocation, as the i.MX25 SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows mx25 to boot again. Acked-By: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx25: Remove empty line after printing the reset causeFabio Estevam2015-01-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there is an unneeded empty line after printing the reset cause: U-Boot 2015.01-rc4-00080-g0551a93 (Jan 06 2015 - 13:04:19) CPU: Freescale i.MX25 rev1.2 at 399 MHz Reset cause: POR Board: MX25PDK I2C: ready DRAM: 64 MiB MMC: FSL_SDHC: 0 Remove the extra "\n" when printing the reset cause. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | ARM: UniPhier: add UART initialization routine for low-level debugMasahiro Yamada2015-01-08-0/+128
| | | | | | | | | | | | | | | | | | | | | | The low-level debugging functions are useful to debug the early boot stage where the full UART driver is not available. UniPhier SoCs need to initialize the UART port 0 to use this feature. The initialization routine is called at the very entry of the lowlevel_init(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: enable output of system busMasahiro Yamada2015-01-08-0/+15
| | | | | | | | | | | | | | | | For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs, the output of the system bus is disabled by default. It must be enabled by software to have access to the system bus. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: fix SRAM size on support cardMasahiro Yamada2015-01-08-3/+3
| | | | | | | | | | | | | | | | | | | | The max size of available memories on slot0 and slot1 is 32MB because - EA[25] signal is not output on the save-pin mode which is used PH1-LD4 or later SoCs. - EA[25] signal is not connected by the limitation (or bug?) of the PLD logic of DCC support card. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'misc' of git://git.denx.de/u-boot-x86Tom Rini2015-01-05-113/+9
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| * | cros-ec-keyboard: Synchronize DT binding from linuxSjoerd Simons2015-01-05-113/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ChromeOS EC keyboard is used by various different chromebooks. Peach pi being the third board in the u-boot tree to use it (snow and peach pit the other two). Rather then embedding the same big DT node in the peach-pi DT again, copy the dtsi snippit & bindings documentation from linux and include it in all 3 boards. This slightly changes the dt bindings in u-boot: * google,key-rows becomes keypad,num-rows * google,key-colums becomes keypad,num-colums * google,repeat-delay-ms and google,repeat-rate-ms are no longer used and replaced by hardcoded values (similar to tegra kbc) Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | keystone: set default pci mode to root complexKaricheri, Muralidharan2015-01-05-0/+34
| | | | | | | | | | | | | | pci ports are used as root complex in Linux. So set this as default in u-boot for keystone devices Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
* | arm: omap: reset sata on bootDmitry Lifshitz2015-01-05-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP platforms (like OMAP5) Linux kernel fails to detect a SATA device if it is used by U-Boot. It happens because U-Boot does not reset SATA controller before boot. Reset the controller on OS boot so that Linux will have a clean state to work with. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* | OMAP5+: sata/scsi: implement scsi_bus_reset()Dmitry Lifshitz2015-01-05-0/+6
| | | | | | | | | | | | | | | | Implement missing scsi_bus_reset() for SCSI subsystem commands on OMAP platforms. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* | Revert "ARM: omap4: Update sdram setting for panda rev A6"Nishanth Menon2015-01-05-4/+0
| | | | | | | | | | | | This reverts commit 47a4bea6af77b01d59a410d09a4c34b2dd14cf50. Signed-off-by: Nishanth Menon <nm@ti.com>
* | ARM: OMAP4: Panda: rework DMM logicNishanth Menon2015-01-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of DMM logic is reuse from commit 47a4bea6af77b01d59a410d09a4c34b2dd14cf50 ("ARM: omap4: Update sdram setting for panda rev A6") Which broke SDP4430 with ES2.3 (uses old DDR). So, to maintain support for newer DDR used in Panda ES rev B3, we should, in addition to the commit 675cc77a3ae45e8b0ec17128563264d4a509f628 ("ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAM"), DDR timings, also do DMM configuration specific to Panda. Signed-off-by: Nishanth Menon <nm@ti.com>
* | omap-common/hwinit-common.c: timer_init() doesn't need to touch gdTom Rini2015-01-05-5/+0
| | | | | | | | | | | | | | | | | | | | The gd will be cleared at first so we don't need to set arch.tbl to 0. In addition, the checks later against lastinc also work fine with an initial value of 0 here. This also brings us in line with sunxi code for example. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | am33xx: Drop timer_init call from s_initTom Rini2015-01-05-1/+0
| | | | | | | | | | | | | | | | In both SPL and non-SPL cases we will make a call to timer_init() early on and do not need to call it again within s_init(). Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | socfpga: Drop redundant save_boot_paramsTom Rini2015-01-05-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | The save_boot_params function here is the same as the default weak one from arch/arm/cpu/armv7/start.S, drop. Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | ARM: bootm: do not add PSCI to fdt when booting in secure mode.Ian Campbell2015-01-05-2/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8bc347e2ec17 "ARM: bootm: Allow booting in secure mode on hyp capable systems" added the capability to select nonsec vs sec mode boot via an environment var. There is a subtle gotcha with this functionality, which is that the PSCI nodes are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting in secure mode. Which means that if the kernel is PSCI aware then it will fail to boot because it will try and do PSCI from secure world, which won't work. This likely didn't get noticed before because the original purpose was to support booting the legacy linux-sunxi kernels which don't understand PSCI. To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and use from the virt-dt code. As well as avoiding the creation of the PSCI nodes we should also avoid reserving the secure RAM, so do so. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-6/+57
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| * arm:mx6sx add QSPI supportPeng Fan2014-12-31-6/+57
| | | | | | | | | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-7/+2693
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| * | ARM: Implement non-cached memory supportThierry Reding2014-12-18-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on Jetson TK1Thierry Reding2014-12-18-0/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes the second root port to a miniPCIe slot. Enable the PCIe controller and the network driver to allow the device to boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra124 PCIe device tree nodeThierry Reding2014-12-18-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra124 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add GIC for Tegra124Thierry Reding2014-12-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC v2 found on the Cortex-A15 CPU complex of Tegra124. U-Boot doesn't use this but subsequent patches will add device tree nodes that reference it by phandle. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on BeaverThierry Reding2014-12-18-0/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Beaver has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. In addition the board has a mini-PCIe expansion slot. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on CardhuThierry Reding2014-12-18-0/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC is available on the dock over the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra30 PCIe device tree nodeThierry Reding2014-12-18-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra30 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add GIC for Tegra30Thierry Reding2014-12-18-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use it directly but subsequent patches will add device tree nodes that reference it by phandle. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on TrimSliceThierry Reding2014-12-18-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add Tegra20 PCIe device tree nodeThierry Reding2014-12-18-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra20 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable XUSB pad controller on Jetson TK1Thierry Reding2014-12-18-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PCIe and SATA lane configuration to the Jetson TK1 device tree, so that the XUSB pad controller can be appropriately configured. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Add XUSB pad controller on Tegra124Thierry Reding2014-12-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA lanes. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement XUSB pad controllerThierry Reding2014-12-18-0/+781
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement powergate supportThierry Reding2014-12-18-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the powergate API that allows various power partitions to be power up and down. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Provide PCIEXCLK reset IDThierry Reding2014-12-18-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement tegra_plle_enable()Thierry Reding2014-12-18-0/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: colibri_t30: comment style fixMarcel Ziswiler2014-12-18-4/+8
| |/ | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-30-1/+11
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| * | arm: socfpga: Change watchdog timeoutStefan Roese2014-12-21-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current current watchdog timeout of 12 seconds is a bit small for booting into Linux, especially when using a NFS based rootfs. So lets change this timeout to a more defensive value of 30 seconds. Also we now call the hw_watchdog_init() function so that we override the value already configured from the Preloader. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-30-18/+13
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| * | | imx: i2c: Zap unnecessary malloc() callsMarek Vasut2014-12-30-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The malloc() calls are unnecessary, just allocate the stuff on stack. While at it, reorder the code a little, so that only one variable is used for the text, use snprintf() instead of sprintf() and use %01d as a formatting string to avoid any possible overflows. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | | imx SPL: enable boot from eMMC boot partitions.Pierre Aubert2014-12-30-1/+3
| | | | | | | | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
| * | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2014-12-30-116/+168
| |\ \ \ | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | | imx:mx6 fix return value of mxc_get_clockPeng Fan2014-12-19-1/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mxc_get_clock's return type is unsigned int. 'return -1' is same with 'return 0xffffffff', so 0 should be used as the return value when unsupported mxc_clock type is passed to mxc_get_clock. Also include an err message when unsupported mxc_clock type is passed to mxc_get_clock. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-12-30-3/+826
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| * | | | ARM: UniPhier: display boot swap pin status by pinmon commandMasahiro Yamada2014-12-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This information would be useful enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add dump command of DDR PHY parametersMasahiro Yamada2014-12-30-0/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a dump command of DDR PHY parameters of UniPhier SoC family. It might not be used very often for the regular operation but it would be useful when something goes wrong with DDR memories. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-08-24 21:08:53 +0000