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* ARM: AM33xx: Cleanup clocks layerLokesh Vutla2013-08-15-219/+174
| | | | | | | | | | | Cleaning up the clocks layer. This helps in addition of new Soc with minimal changes. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* ARM: AM33xx: Cleanup dplls dataLokesh Vutla2013-08-15-182/+227
| | | | | | | | | | | | | Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* am335x_evm: Add support to boot from NOR.Steve Kipisz2013-07-30-2/+6
| | | | | | | | | | | | | | | | | | NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c with TI81xx checks as at this time U-Boot does not discard unused sections in the main build and this code relies on functions specific to (and only provided in) ti81xx-related code. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am335x_evm: Add support for the NOR module on the memory capeSteve Kipisz2013-07-30-0/+13
| | | | | | | | | | | This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Clean up config changes slightly] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct gpmc_cfg->irqstatus/enableTom Rini2013-07-30-2/+2
| | | | | | | | Based on our usage of the GPMC, either with NOR or NAND we do not need to be setting the irqstatus or irqenable bits and should clear them like we have historically. Signed-off-by: Tom Rini <trini@ti.com>
* ARM: DRA7xx: Add CPSW support to DRA7xx EVMMugunthan V N2013-07-26-0/+40
| | | | | | Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: DRA7xx: Enable GMAC clock controlMugunthan V N2013-07-26-1/+12
| | | | | | Enabling CPSW module by enabling GMAC clock control Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: DRA7xx: Lock DPLL_GMACLokesh Vutla2013-07-26-0/+32
| | | | | | | | | Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* omap3/sys_info: fix printout of OMAP36XX L3 freqencyAndreas Bießmann2013-07-26-3/+3
| | | | | | | | | The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz used by OMAP34xx/OMAP35xx. Also fix checkpatch warning about alignment. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm: omap3: spl: Fix problem with 8bit NAND devicesStefan Roese2013-07-26-0/+12
| | | | | | | | Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit access. This patch adds support for 8bit NAND devices as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
* Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD2013-07-25-11762/+795
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| * Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-24-4/+22
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| | * vf610: Add I2C support for Vybrid VF610 platformAlison Wang2013-07-23-0/+14
| | | | | | | | | | | | | | | | | | | | | This patch adds I2C support for Vybrid VF610 platform and adds I2C0 support to VF610TWR board. Signed-off-by: Alison Wang <b18965@freescale.com>
| | * i2c, soft-i2c: switch to new multibus/multiadapter supportHeiko Schocher2013-07-23-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | - added to soft_i2c driver new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org>
| | * i2c: common changes for multibus/multiadapter supportHeiko Schocher2013-07-23-1/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Cc: Henrik Nordström <henrik@henriknordstrom.net>
| * | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-11758/+773
| |/ | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* | ARM: highbank: avoid bss write in timer_initRob Herring2013-07-25-2/+0
| | | | | | | | | | | | | | | | | | The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | ARM: highbank: set timer prescaler to 256Rob Herring2013-07-25-2/+6
| | | | | | | | | | | | | | The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | ARM: highbank: fix get_tbclk value to timer rateRob Herring2013-07-25-1/+1
| | | | | | | | | | | | get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | ARM: move interrupt_init to before relocationRob Herring2013-07-25-2/+1
|/ | | | | | | | | interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* Build arch/$ARCH/lib/bootm.o depending on CONFIG_CMD_BOOTMDirk Eibach2013-07-16-1/+1
| | | | | | | | MAKEALL is fine for ppc4xx and mpc85xx. Run checks were done on our controlcenterd hardware. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Andy Fleming <afleming@freescale.com>
* arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.Łukasz Majewski2013-07-16-5/+4
| | | | | | | | | | | Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board). Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-07-12-182/+5446
|\ | | | | | | | | | | | | | | | | | | Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and serial. Conflicts: arch/arm/dts/exynos5250.dtsi Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114Jim Lin2013-07-11-139/+532
| | | | | | | | | | | | | | | | | | | | Tegra30 and Tegra114 are compatible except PLL parameters. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: Tegra: FDT: Add USB EHCI function for T30/T114Jim Lin2013-07-11-0/+54
| | | | | | | | | | | | | | | | | | | | Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards. Signed-off-by: Jim Lin <jilin@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-07-10-15/+3249
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| | * arm: exynos: fix clock calculationMinkyu Kang2013-07-09-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
| | * EXYNOS: Move files from board/samsung to arch/armRajeshwari Shinde2013-07-05-10/+3081
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch performs the following: 1) Convert the assembly code for memory and clock initialization to C code. 2) Move the memory and clock init codes from board/samsung to arch/arm 3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code 4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5. 5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main. 6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250. TEST: Tested SD-MMC boot on SMDK5250 and Origen. Tested USB and SPI boot on SMDK5250 Compile tested for SMDKV310. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS4210: Configure GPIO for uartRajeshwari Shinde2013-07-05-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch configures the gpio values for UART on Origen and SMDKV310 using pinmux Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS: Add API for power reset and exit wakeupRajeshwari Shinde2013-07-05-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds APIs to get power reset status and exit the wakeup condition for both exynos5 and exynos4 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * SMDK5250: Remove reduntant codeRajeshwari Shinde2013-06-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enum boot_mode is defined twice once in spl.h and also in spl_boot.c, hence removing the same from spl_boot.c and including the header file. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5: FDT: Add serial device node valuesRajeshwari Shinde2013-06-24-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the device node required for serial driver Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5Axel Lin2013-07-02-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs. These SoCs have different gpio count but currently omap_gpio driver uses hard coded 192 which is wrong. This patch fixes this issue by: 1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h. 2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5. Thanks for Lubomir Popov to provide valuable comments to fix this issue. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | ARM: OMAP4+: Fix MA detection during SDRAM_AUTO_DETECTIONLokesh Vutla2013-07-02-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During SDRAM_AUTO_DETECTION MA is not configured. For Soc's > OMAP4460 MA is present. So populating MA for the same. Tested on OMAP4430 PANDA, OMAP4460 PANDA. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | am33xx: fix the ddr_cmdtctrl structureIlya Ledvich2013-07-02-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the wrong mapping between the DDR I/O control registers on AM33XX SoCs and the software representation in the SPL code. The most recent public TRM defines the following DDR I/O control registers offsets: * ddr_cmd0_ioctrl : offset 0x44E11404 * ddr_cmd1_ioctrl : offset 0x44E11408 * ddr_cmd2_ioctrl : offset 0x44E1140C * ddr_data0_ioctrl: offset 0x44E11440 * ddr_data1_ioctrl: offset 0x44E11444 While the struct ddr_cmdtctrl has also some reserved bits in the beginning. The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc. Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because of this mapping mismatch. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-28-23/+1581
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| | * | mx27: add i2c clocktrem2013-06-26-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org> Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
| | * | mx27: add function enable_cachestrem2013-06-26-0/+8
| | | | | | | | | | | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
| | * | imx: Complete the pin definitions for the i.MX6DL / i.MX6SoloPierre Aubert2013-06-26-22/+1569
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de>
| | * | imx6: fix GPR2 wrong definitionPierre Aubert2013-06-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Dirk Behme <dirk.behme@gmail.com>
| * | | pxa: fix memory coherency problem after relocationMike Dunn2013-06-22-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the xscale, the icache must be invalidated and the write buffers drained after writing code over the data bus, even if the caches are disabled. Tested on the pxa270. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
| * | | pxa: use -mcpu=xscale compiler optionMike Dunn2013-06-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will cause gcc to define the __XSCALE__ macro. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
| * | | pxa: turn icache off in cpu_init_crit()Mike Dunn2013-06-22-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The comment in the low-level initialization function cpu_init_crit() says that the caches are being disabled, but (oddly) the icache is actually turned on. This is probably not a good idea prior to relocating code, so this patch turns it off. Tested on the pxa270. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
* | | | bootm: Clean up bootz_setup() functionSimon Glass2013-07-10-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function has no prototype in the headers and passes void * around, thus requiring several casts. Tidy this up. - Add new patch to clean up bootz_setup() function Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | exynos: Avoid function instrumentation for microsecond timerSimon Glass2013-06-26-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For tracing to work it has to be able to access the microsecond timer without causing a recursive call to the function entry/exit handlers. Add attributes to the relevant functions to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | arm: Implement the 'fake' go commandSimon Glass2013-06-26-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement this feature on ARM for tracing. It would be nice to have generic bootm support so that it is easily implemented on any arch. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | | cros: exynos: add cros-ec device nodes to exynos5250-snow.dtsHung-ying Tyan2013-06-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds cros-ec related device nodes to exynos5250-snow.dts. It also adds a gpio node to exynos5250.dtsi. Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-22-127/+262
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| * | | arm: optimize relocate_code routineAlbert ARIBAUD2013-06-21-20/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use section symbols directly Drop support for R_ARM_ABS32 record types Eliminate unneeded intermediate registers Optimize relocation table iteration Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | arm: make __rel_dyn_{start, end} compiler-generatedAlbert ARIBAUD2013-06-21-13/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is only done where needed: some linker scripts may contain relocation symbols yet remain unchanged. __rel_dyn_start and __rel_dyn_end each requires its own output section; putting them in relocation sections changes their flags and breaks relocation. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
generated by cgit v1.1 at 2024-08-23 22:33:33 +0000