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* ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-11-260/+198
| | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-11-895/+869
| | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-11-1205/+1312
| | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: emif: Detect SDRAM from SDRAM config registerLokesh Vutla2013-03-11-7/+28
| | | | | | | | | | | Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* Allow AM33xx boards to setup GPMC chipselects.Mark Jackson2013-03-11-0/+2
| | | | | | | | | | | | | | | | Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects. Changes in V4: - Fix checkpatch errors (TAB -> space mangling) Changes in V3: - Fix line wrapping Changes in V2: - Indicate this is for AM33xx (not OMAP2) Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
* OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.Enric Balletbo i Serra2013-03-11-1/+1
| | | | | | In order to use SPL boot from OneNAND we should initialize the gpmc. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* SPL: ONENAND: Fix some ONENAND related defines.Enric Balletbo i Serra2013-03-08-5/+5
| | | | | | | | Some ONENAND related defines use the term ONE_NAND instead of ONENAND, as the technology name is ONENAND this patch replaces all these defines. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* omap3: allow dynamic selection of gfx_formatNikita Kiryanov2013-03-08-0/+1
| | | | | | | | | | | | | | | | | Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded in the code. This forces anyone who wants to use a different gfx_format to make adjustments after calling omap3_dss_panel_config(). This could be avoided if the value of gfx_format were parameterized as input for omap3_dss_panel_config(). Make gfx_format a field in struct panel_config, and update existing structs to set this field to the value that was originally hard coded. Cc: Wolfgang Denk <wd@denx.de> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* omap3: add useful dss definesNikita Kiryanov2013-03-08-0/+30
| | | | | | | | | | | | Add useful omap3 dss defines for: polarity, TFT data lines, lcd display type, gfx burst size, and gfx format Cc: Anatolij Gustschin <agust@denx.de> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* omap_hsmmc: add driver check for write protectionNikita Kiryanov2013-03-08-7/+8
| | | | | | | | Add check for write protection in omap mmc driver. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* omap_hsmmc: implement driver check for card detectionNikita Kiryanov2013-03-08-7/+7
| | | | | | | Implement driver check for card detection. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* omap: consolidate common mmc definitionsNikita Kiryanov2013-03-08-551/+175
| | | | | | | | | The various mmc_host_def.h files are almost identical. Reduce code duplication by moving the similar definitions to a common header file. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* am33xx: Update DDR3 EMIF configuration sequenceTom Rini2013-03-08-3/+9
| | | | | | | | | | Based on http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips we need to re-work our sequence in config_sdram slightly to match what the TRM describes as the correct sequence. In our current (incorrect) sequence some edge cases may fail to initalize correctly. Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-02-21-0/+8
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| * am33xx: support for booting via usbethIlya Yanok2013-02-18-0/+4
| | | | | | | | | | | | | | | | This patch adds BOOT_DEVICE define for USB booting and fixes spl_board_init function to call arch_misc_init (this is the place there musb is initialized). Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * da8xx: Add the missing pinmux for da830 to the gpio driverTomas Novotny2013-02-18-0/+4
| | | | | | | | | | | | | | | | | | The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of kernel version 3.7.5. If the driver is used for the da850, then SoC variant must be specified by CONFIG_SOC_DA850. Signed-off-by: Tomas Novotny <tomas@novotny.cz> Cc: Tom Rini <trini@ti.com>
* | Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'Albert ARIBAUD2013-02-21-1/+206
|\ \ | |/ |/| | | | | | | | | | | This pulls the three following ZYNQ commits into ARM master: 7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board 59c651f4: arm: zynq: Add SLCR support with system reset 00ed3458: arm: zynq: Add lowlevel initialization to C
| * arm: zynq: Add lowlevel initialization to CMichal Simek2013-02-07-2/+70
| | | | | | | | | | | | | | Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm: zynq: Add SLCR support with system resetMichal Simek2013-02-07-0/+137
| | | | | | | | | | | | | | | | | | The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-1219/+9426
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| * | arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the READMELucas Stach2013-02-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com>
| * | Tegra114: Dalmore: Add DT filesTom Warren2013-02-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra114: Add common CPU (shared) filesTom Warren2013-02-11-4/+1291
| | | | | | | | | | | | | | | | | | These files are used by both SPL and main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra114: Add CPU (armv7) filesTom Warren2013-02-11-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | These files are for code that runs on the CPU (A15) on T114 boards. At this time, there is no A15-specific code here. As T114-specific run-time code is added, it'll go here. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra114: Add AVP (arm720t) filesTom Warren2013-02-11-38/+403
| | | | | | | | | | | | | | | | | | | | | This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra114: Add arch-tegra114 include filesTom Warren2013-02-11-5/+1365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra: add SPI SLINK driverAllen Martin2013-02-11-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: add addresses of SPI SLINK controllersAllen Martin2013-02-11-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add I/O addresses of SPI SLINK controllers 1-6 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra30: fdt: add SPI SLINK nodesAllen Martin2013-02-11-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | Add tegra30 SPI SLINK nodes to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra30: add SBC1 to periph id mapping tableAllen Martin2013-02-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | SBC1 is SPI controller 1 on tegra30 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra20: fdt: add SPI SFLASH nodeAllen Martin2013-02-11-0/+12
| | | | | | | | | | | | | | | | | | | | | Add node for tegra20 SPI SFLASH controller to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: rename FUNCMUX_UART2_UARTBStephen Warren2013-02-11-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | FUNCMUX_ defines should be named after the pin groups they affect, not after the module they're muxing onto those pin groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.cTom Warren2013-02-11-1188/+768
| | | | | | | | | | | | | | | | | | | | | | | | | | | This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entryTom Warren2013-02-11-8/+0
| | | | | | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Add DDR3 support for AM335x-EVM (Version 1.5A)Jeff Lance2013-02-07-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the DDR3 chip. [Hebbar Gururaja <gururaja.hebbar@ti.com>] - Resolve merge conflict while rebasing. File structure is changed in the mainline. So re-arrange the code accordingly. - Update commit message to reflect the DDR3 part number Signed-off-by: Jeff Lance <j-lance1@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
| * | pcm051: Add support for Phytec phyCORE-AM335xLars Poeschel2013-02-07-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board is named pcm051 and has this hardware: SOC: TI AM3359 DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB ETH 1: LAN8710AI SPI-Flash: W25Q64BVSSIG RTC: RV-4162-C7 I2C-EEPROM: CAT32WC32 NAND: MT29F4G08_VFPGA63 PMIC: TPS65910A3 LCD Supported: UART 1 MMC/SD ETH 1 USB I2C SPI Not yet supported: NAND RTC LCD Signed-off-by: Lars Poeschel <poeschel@lemonage.de> [trini: Add #define CONFIG_PHY_ADDR 0 to config] Signed-off-by: Tom Rini <trini@ti.com>
| * | am33xx: add a pulldown macro to pinmux configLars Poeschel2013-02-07-1/+2
| | | | | | | | | | | | Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
| * | ARM: add wfi assembly macroRob Herring2013-02-03-0/+6
| | | | | | | | | | | | | | | | | | | | | Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-02-02-70/+1435
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| | * | mxs: mmc: Allow overriding default card detect implementationMarek Vasut2013-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some MXS based boards do not implement the card-detect signal. Allow user to specify alternate card-detect implementation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * | mxs: ssp: Add SSP registers map for MX23Marek Vasut2013-01-28-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 SSP register layout differs from MX28 in certain bits, adjust the register layout accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * | mxs: dma: Fix APBH DMA driver for MX23Marek Vasut2013-01-28-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 has less channels for the APBH DMA, sligtly different register layout and some bits in those registers are placed differently. Reflect this in the driver. This patch fixes MMC/DMA issue on MX23. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * | mxs: Use __weak annotation to simplify codeFabio Estevam2013-01-28-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the __weak annotation can make the code cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * | mxs: Boost the memory power supplyMarek Vasut2013-01-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory power supply on MX23 didn't pump out enough juice into the DRAM chip, thus caused occasional memory corruption. Fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * | imximage.cfg: run files through C preprocessorTroy Kisky2013-01-22-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The '#' used as comments in the files cause the preprocessor trouble, so change to /* */. The mkimage command which uses this preprocessor output was moved to arch/arm/imx-common/Makefile .gitignore was updated to ignore .cfgtmp files. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| | * | mxs: Add MX23 quirks into the clock codeOtavio Salvador2013-01-21-11/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * | mxs: Fix the memory init for MX23Otavio Salvador2013-01-21-15/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory init is slightly different on MX23, thus split the memory init for mx23 and mx28 into different functions. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * | mxs: Add function to ungate the power block on MX23Marek Vasut2013-01-21-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power block on MX23 must first be ungated before it can be operated. Add function to MXS power init that ungates it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * | mx23: config: Enable building of u-boot.sb binaryOtavio Salvador2013-01-21-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For i.MX23 we need to pass imx23 as elftosb param. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * | mx23: SPL: Initialize DDR at 133MHzOtavio Salvador2013-01-21-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-08-23 23:05:06 +0000