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* mx6: Fix use of improper value in enable_ipu_clockPierre Aubert2013-11-22-1/+1
| | | | | | | | | | | | The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize the CCGR3 register caused an undefined value for CG0. Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com> (cherry picked from commit a0a0dacfe8ff8d7036db823ca5ea9ba393a35187) Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit c6fb5f07f5530b0db3157141e14cc056aa3a904f)
* imx: nitrogen6x: mx6qsabrelite: Add support for DVI monitorsRobert Winkler2013-11-22-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | A little background is probably appropriate for this patch. Since "the beginning" of usage of the SABRE Lite and Nitrogen6x boards, DVI detection has been somewhat broken. Some (most) DVI monitors don't produce the "HPD" bit in the PHY_STAT0 register, but do show proper toggling of the RX_SENSE0..3 bits. Creating a new the bit-mask to include all five bits and modifying the 'hdmidet' command and internal detection routines allows these monitors to function properly in U-Boot. A related patch to our kernels allows things to work under Linux: https://github.com/boundarydevices/linux-imx6/commit/7d8752905c118af9063738a533227de0b2f6ecd4 Signed-off-by: Robert Winkler <robert.winkler@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de> (cherry picked from commit 10f779da54b8a8c85df6d58592c40836d8e7ed49) Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit c5f576bb0effceb232986d1b6ca76f06f129516f)
* mx6: Factor out common HDMI setup codePardeep Kumar Singla2013-11-22-1/+57
| | | | | | | | | | | | | | | Instead of duplicating HDMI setup code for every mx6 board, factor out the common code Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com> Acked-By: Eric Nelson <eric.nelson@boundarydevices.com> (cherry picked from commit 5ea7f0e328c19542ce96d8242125b51b3dbca86b) Conflicts: arch/arm/cpu/armv7/mx6/soc.c arch/arm/include/asm/arch-mx6/clock.h Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit e968e5301c42d2c2071f9ef871cfee8200e58b11)
* imx6: fix GPR2 wrong definitionPierre Aubert2013-11-22-1/+1
| | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Dirk Behme <dirk.behme@gmail.com> (cherry picked from commit 7aa1e8bb1bdbcc9d6114f70504257c2eae4b0cd7) Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 68c9ed925b8f07d3050765efc2eadd0098a247fe)
* ENGR00288418 Add EPDC splash screen for MX 6DL SabreSD and 6SL EVKRobby Cai2013-11-21-0/+48
| | | | | | | | | | | | | | | | | Add EPDC splash screen feature for MX6SL EVK, and MX6DL SABRESD board. - Currently, splash screen consists of a simple black border around a white screen. Done this way to save in memory footprint. - EPDC splash screen is disabled by default in the config file for MX6DL_SABRESD and MX6SL_EVK. If left enabled, the U-Boot image will not boot correctly (hang), since some additional content on the boot device (waveform file) is required for EPDC splash to work correctly. Please refer to Linux Reference Manual for how to flash WAVEFORM file. Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit b934091a04e11e96281b10cf63830851fd096fdd)
* ENGR00287831 mx6: fix the secure boot issue on the new tapout chipJason Liu2013-11-15-15/+81
| | | | | | | | | | The new TO(i.MX6Q TO1.5 and i.MX6DL TO1.2) of ROM change the HAB API table address, thus the secure boot can't boot up on the new TO. This patch fix this issue by fix up the HAB API table address according to the TO revision. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00288025 imx6: fix build warningsRobin Gong2013-11-14-1/+1
| | | | | | | | | | | | | | Fix below two warning: soc.c: In function 'check_1_2G': soc.c:488:2: warning: suggest parentheses around comparison in operand of '&' [-Wparentheses] main.c: In function 'main_loop': main.c:444:3: warning: implicit declaration of function 'set_default_env' [-Wimplicit-function-declaration] set_default_env("Use default environment for mfgtools\n"); Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00287923 fix random hang when download by mfgtoolsFrank Li2013-11-14-0/+2
| | | | | | | | ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00285890 imx6:plugin: update the ROM_API_TABLE_BASE_ADDR for plugin codeJason Liu2013-11-05-3/+22
| | | | | | | | | | | | | | i.MX6DQ TO1.5 and i.MX6DL/SOLO change the ROM_API_TABLE_BASE_ADDR from 0xc0 to 0xc4.Need update the plugin code to sync with this change. The change as the following for the new TO with i.MX6DQ, i.MX6DL/SOLO: For i.MX6DQ, if the TO >=1.5, will use the new ROM_API_TABLE_BASE_ADDR=0xc4 For i.MX6DL/S, if the TO >=1.2, will use the new ROM_API_TABLE_BASE_ADDR=0xc4 For the old TO, we will still use the 0xc0 to keep compatible. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00278711: ARM: mx6: use working_fdt instead of 'images.ft_addr'Robin Gong2013-09-09-2/+2
| | | | | | | | | If we use 'bootz' to boot kernel, u-boot will not touch the global 'images', but in both 'bootm' and 'bootz' will use 'working_fdt' as the fdt load address. So we replace 'images.ft_addr' with 'working_fdt' to support 'bootz' and 'bootm'. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00278692 ARM: mx6: use hang() instead of do_reset when wrong dtb file usedRobin Gong2013-09-09-2/+2
| | | | | | Use hang() instead of do_reset, so that we can easily see what error happen. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00278511: ARM: mx6: get fdt_blob from images instead of 'fdt_addr' paramRobin Gong2013-09-06-4/+19
| | | | | | | | | | --Get fdt_blob from images.ft_addr which set by boot command instead of 'fdt_addr' param, so that we can use any other name as fdt load address. --If find it's not ldo-enable dts on 1.2G chip, will report the error log and reset board to correct the dtb file. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00277992 Auto check if boot from usbFrank Li2013-09-04-0/+5
| | | | | | | If boot from usb, reset environment to default value. Auto apply mfgtools setting and boot mfgtools kernel. Signed-off-by: Frank Li <Frank.li@freescale.com>
* ENGR00277895-2 ARM: mx6: check the property setting of "fsl,ldo-bypass"Robin Gong2013-09-04-5/+9
| | | | | | | | | | Check the right property setting of "fsl,ldo-bypass" in dts to know what ldo mode we need use(ldo-bypass or ldo-enable). Before only check the presence of "fsl,ldo-bypass", now change to check whether "fsl,ldo-bypass = <1>" in dts. If yes, switch to ldo-bypass mode. If "fsl,ldo-bypass = <0>" or no "fsl, ldo-bypass" property, u-boot keep in ldo-enable mode. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00277895-1: ARM: mx6: add waring message to use ldo-enable dts on 1.2G chipRobin Gong2013-09-04-2/+4
| | | | | | | We need add clear warning message to remind useing ldo-enable dts for 1.2G chip . Correct 1.2G check code too. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00276023-3: ARM: mx6: enable ldo bypass check on mx6 boardRobin Gong2013-09-02-0/+4
| | | | | | | Enable ldo bypass check on mx6 and get fdt->blob from 'fdt_addr' which contained the right fdt. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00276023-1: ARM: imx: add ldo bypass and 1.2G checkRobin Gong2013-08-29-2/+56
| | | | | | | Add ldo bypass and 1.2G check in soc.c. Extend arch_preboot_os to support read ldo-bypass from fdt. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00275348-7 imx6: add secureboot supportJason Liu2013-08-21-0/+379
| | | | | | This patch add the secureboot support Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00275348-3 imx6: add the core plugin helper function supportJason Liu2013-08-21-0/+108
| | | | | | This patch add the core plugin helper function support Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00275348-1 imx6: turn on L2 cache supportJason Liu2013-08-21-0/+20
| | | | | | This patch is to turn on the L2 cache support Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00275413-01: ARM: MSL: add i2c0 support for imx6sl evkFugang Duan2013-08-15-0/+5
| | | | | | | - Add i2c0 support for imx6sl evk platform. - Read pmic device ID and revsion ID. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00275369-02: mx6sl: add fec pad config and initial code for evkFugang Duan2013-08-15-0/+17
| | | | | | Add imx6sl evk fec pad config and fec initial code. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00275369-01: mx6sl: add fec clock enable interfaceFugang Duan2013-08-15-0/+34
| | | | | | Add fec clock enable interface in clock.c file. Signed-off-by: Fugang Duan <B38611@freescale.com>
* mx6: Add solo-lite variant supportFabio Estevam2013-08-07-3/+133
| | | | | | | | | | mx6 solo-lite is another member of the mx6 series. For more information about mx6 solo-lite, please visit: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00264076-5 i.mx6:shutdown vddpu and pcie phy to save powerJason Liu2013-05-24-0/+30
| | | | | | | shutdown vddpu and pcie phy to save power Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00264076-3 i.mx6:gate/ungate PFD before using itJason Liu2013-05-24-0/+38
| | | | | | | | | Per the IC design, we need to gate/ungate all the unused PFDs to make sure PFD is working correctly, otherwise, PFDs may not not output clock after reset. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00264076-2 i.mx6:Add the CPU temperature supportJason Liu2013-05-24-3/+692
| | | | | | | | The patch add the CPU thermal temperature support. Use universal equation for all i.MX6 series SOCs. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00264076-1 i.mx6:reset LDOs step_timeJason Liu2013-05-24-1/+9
| | | | | | | | | | | | | ROM may modify CORE's LDO step_time settings according to the fuse setting for safe, reset them to the default value.Reset it to 0'b00. 0'b00: 64 cycles of 24M clock; 0'b01: 128 cycles of 24M clock; 0'b02: 256 cycles of 24M clock; 0'b03: 512 cycles of 24M clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00263305-14 i.mx6:sabreauto: Add the GPMI nand supportJason Liu2013-05-21-3/+6
| | | | | | Add the GPMI nand support Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00263305-13 mtd: mxs_nand: Add support for i.MX6Stefan Roese2013-05-21-0/+17
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* ENGR00263305-12 dma: Add i.MX6 support to drivers/dma/apbh_dma.cStefan Roese2013-05-21-1/+32
| | | | | | | | | This will be used by the i.MX6 NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* ENGR00263305-11 imx: Move some i.MX common functions into the imx-common ↵Stefan Roese2013-05-21-63/+97
| | | | | | | | | | | | | | | | | | | | directory This patch moves the following functions into the imx-common directory: - mxs_wait_mask_set() - mxs_wait_mask_clr() - mxs_reset_block() These are currently used by i.MX28. But the upcoming GPMI NAND port for i.MX6 will also use these functions. So lets move them to a common location to re-use them. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* ENGR00263305-10 imx: Move some header files from arch-mxs to imx-commonStefan Roese2013-05-21-20/+20
| | | | | | | | | | | | | | | | | | | The following headers are moved to a i.MX common location: - regs-common.h - regs-apbh.h - regs-bch.h - regs-gpmi.h - dma.h This way this header can be re-used also by other i.MX platforms. For example the i.MX6 which will need it for the upcoming NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* ENGR00263305-3 i.mx6:sabresd: Add the initial i.MX6dl sabresd board supportJason Liu2013-05-21-132/+1662
| | | | | | | | | | This patch is to add the initial Freescale i.MX6dl sabresd board support. - The DDR script has been updated to the v1.5 version from ddr-scripts-rel commit: bfd157a Updated MX6DL and MX6DQ ARD and SabreSD scripts. - i.mx6dl sabre-sd board shared the same design with i.mx6q sabre-sd board except the SOC is different.Thus, we can use the same board file. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00263305-2 i.mx:i.mx6q: factor out the common iomux pad ctrl definitionJason Liu2013-05-21-27/+29
| | | | | | | This patch is to factor out the common iomux pad ctrl definition. No function change at all. Signed-off-by: Jason Liu <r64343@freescale.com>
* exynos: Correct use of 64-bit divisionSimon Glass2013-04-17-1/+6
| | | | | | | | | | | | | The current code is causing errors like this on my toolchains: /usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/ ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/ armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o) Use do_div() to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Tegra: Split tegra_get_chip_type() into soc & sku funcsTom Warren2013-04-15-36/+83
| | | | | | | | | | | As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: Fix MSELECT clock divisors for T30/T114.Tom Warren2013-04-15-8/+6
| | | | | | | | | A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra114: Initialize System Counter (TSC) with osc frequencyTom Warren2013-04-15-0/+72
| | | | | | | | | T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Tegra: Configure L2 cache control reg properly.Tom Warren2013-04-15-8/+52
| | | | | | | | | | Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra: Restore cp15 VBAR _start vector write for ARMv7Tom Warren2013-04-15-2/+0
| | | | | | | | | | | | A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53), and caused the old monilithic Tegra builds to hang due to an undefined instruction trap. Previously, the code needed to run on both the AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register. I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but now that we use SPL, and boot the AVP w/o any ARMv7 code, I can revert my change, and make Aneesh's change apply to Tegra. Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: support T33 SKU of Tegra30Stephen Warren2013-04-15-0/+2
| | | | | | | | | | | | | | | | | | | Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically to any other Tegra30. An alternative would be to simply remove the SKU checking from tegra_get_chip_type(); most use of the value most likely simply wants to know the current chip, not the specific SKU. Or, the function could be split into separate tegra_get_chip() and tegra_get_sku() for the cases where differentiation really is required. I wonder whether tegra_get_chip_type() should printf() whenever any unkown chip/SKU is found, although perhaps the function is called so early that the printf() wouldn't actually make it to the UART anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARMv7: start.S: stay in HYP mode if u-boot is entered in itAndre Przywara2013-04-15-3/+7
| | | | | | | | | | The KVM and Xen hypervisors for the Cortex-A15 virtualization implementation need to be entered in HYP mode. Should the primary board firmware already enter HYP mode (Calxeda firmware does that), we should not deliberately drop back to SVC mode. Since U-boot does not use the MMU, running in HYP mode is just fine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* ARM: fix CONFIG_SPL_MAX_SIZE semanticsAlbert ARIBAUD2013-04-14-15/+13
| | | | | | | | | | | | | | | | | | | | Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds as this file is never used for SPL builds. Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds to separately test image (text,data,rodata...) size, BSS size, and full footprint each against its own max, and make Tegra boards check full footprint. Also, output section mmutable is not used in SPL builds. Remove it. Finally, update README regarding the (now homogeneous) semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new CONFIG_SPL_MAX_FOOTPRINT macro. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-0/+2
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| * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | ARM: Fix __bss_start and __bss_end in linker scriptsAlbert ARIBAUD2013-04-13-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ebd1cbc introduced compiler-generated __bss_start and __bss_end__ and commit c23561e7 rewrote all __bss_end__ as __bss_end. Their merge caused silent and harmless but potentially bug-inducing clashes between compiler- and linker- generated __bss_end symbols. Make __bss_end and __bss_start compiler-only, and create __bss_base and __bss_limit for linker-only use. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | BUGFIX: arm: data abort in get_bad_stack_swiTetsuyuki Kobayashi2013-04-13-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | When swi instruction is executed, it is expected to get message "software interrupt" in console and dump registers and reboot, as do_software_interrupt() in arch/arm/lib/interrupts.c. But, actually it causes data abort accessing wrong address in get_bad_stack_swi macro in arch/arm/cpu/v7/start.S. This patch fixes this problem. The same mistake in arch/arm/cpu/{arm1136,arm1176,pxa}/start.S. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-13-9/+9
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| * | omap3: Display MHz instead of mHz on the consoleman.huber@arcor.de2013-04-12-2/+2
| | | | | | | | | | | | | | | | | | The processor is hopefully running with M(ega)Hz and not with m(illi)Hz. Signed-off-by: Manfred Huber <man.huber@arcor.de>
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