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* ARM: uniphier: set up charge pump current for MPLL of LD11 SoCMasahiro Yamada2017-02-23-0/+24
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add simple eMMC load APIs instead of ROM APIMasahiro Yamada2017-02-23-58/+195
| | | | | | | | | | | Re-use of routines embedded in the Boot ROM requires a function pointer table for each SoC. This is not nice in terms of the maintainability in a long run. Implement simple eMMC load APIs that are commonly used for LD11, LD20, and hopefully future SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20Masahiro Yamada2017-02-23-1/+25
| | | | | | | | | | | | | For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device would stay in the reset state until its RST_n pin is deasserted by software. Currently, this is cared by an ad-hoc way because the eMMC hardware reset provider is not supported in U-Boot for now. This code should be re-written once the "mmc-pwrseq-emmc" binding is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoCKotaro Hayashi2017-02-23-2/+8
| | | | | | | | | | If the DRAM clock duty does not meet the allowable tolerance, it is marked in an efuse register. If the register is fused, the boot code should compensate for the DRAM clock duty error. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: simplify code, add git-log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove dram_nr_ch from board parametersMasahiro Yamada2017-02-23-26/+18
| | | | | | | This parameter is redundant because we can know the number of channels by checking if dram_ch[2].size is zero. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework spl_boot_device() and related codeMasahiro Yamada2017-02-23-344/+312
| | | | | | | | The current implementation has ugly switch statements here and there, and duplicates similar code. Rework it using table lookups for SoC data and reduce code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move spl_boot_mode() to a separate fileMasahiro Yamada2017-02-23-24/+35
| | | | | | | | The spl_boot_mode() is unrelated to the other code in this file. Besides, this function is only called from common/spl/spl_mmc.c, so it is reasonable to guard with CONFIG_SPL_MMC_SUPPORT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move MMC code to a separate fileMasahiro Yamada2017-02-23-38/+47
| | | | | | | | | | Currently, arch/arm/mach-uniphier/boot-mode/boot-mode.c is messed up with unrelated code; there is no reason why the "mmcsetn" command must be placed in this file. Split out the MMC code into arch/arm/mach-uniphier/mmc-first-dev.c. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove DRAM base address from board parametersMasahiro Yamada2017-02-23-57/+36
| | | | | | | | | The base address of each DRAM channel can be calculated from other parameters, so does not need hard-coding. What we need is the size of each DRAM channel and DRAM_SPARSE flag to decide the start address of DRAM channel 1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: print Support Card info very lateMasahiro Yamada2017-02-23-7/+4
| | | | | | | | | | | Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), the System Bus is initialized by board_init(). The show_board_info() is called from board_init_f() by default, so the revision register of the Micro Support Card may not be accessed at this point. Show its revision after the System Bus is initialized. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: skip memreserve of unused DRAM bank of LD20Masahiro Yamada2017-02-23-0/+3
| | | | | | | | Now the "for" loop here iterates on the detected memory banks. It must skip unused DRAM banks. Fixes: c995f3a3c526 ("ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoC") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: correct spelling of "invalid"Masahiro Yamada2017-02-23-3/+3
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: skip MEMCONF ch2 parsing if CH2_DISABLE bit is setMasahiro Yamada2017-02-23-1/+1
| | | | | | | If SG_MEMCONF_CH2_DISABLE bit is set, the DRAM channel 2 is unused. The register settings for the ch2 should be ignored. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: revive accidentally removed dcache_disable()Masahiro Yamada2017-02-23-0/+4
| | | | | | | | | Commit a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") accidentally dropped dcache_disable() call. Since then, the SPL of LD11 and LD20 failed to load U-Boot proper. Fixes: a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* flash: complete CONFIG_SYS_NO_FLASH move with renamingMasahiro Yamada2017-02-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is not completed. Finish this work by the tool. During this move, let's rename it to CONFIG_MTD_NOR_FLASH. Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH" than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will make the code more readable. Besides, negative meaning symbols do not fit in obj-$(CONFIG_...) style Makefiles. This commit was created as follows: [1] Edit "default n" to "default y" in the config entry in common/Kconfig. [2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH" [3] Rename the instances in defconfigs by the following: find . -path './configs/*_defconfig' | xargs sed -i \ -e '/CONFIG_SYS_NO_FLASH=y/d' \ -e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/' [4] Change the conditionals by the following: find . -name '*.[ch]' | xargs sed -i \ -e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \ -e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \ -e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \ -e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/' [5] Modify the following manually - Rename the rest of instances - Remove the description from README - Create the new Kconfig entry in drivers/mtd/Kconfig - Remove the old Kconfig entry from common/Kconfig - Remove the garbage comments from include/configs/*.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* cmd: move CONFIG_CMD_UNZIP and CONFIG_CMD_ZIP to KconfigMasahiro Yamada2017-02-08-0/+1
| | | | | | | | | | | | | | CONFIG_CMD_ZIP is not defined by any board. I am moving CONFIG_CMD_UNZIP to defconfig files except UniPhier SoC family. I am the maintainer of UniPhier platform, so I know "select CMD_UNZIP" is better for this platform. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ARM: uniphier: compile board data only for SPLMasahiro Yamada2017-01-29-1/+1
| | | | | | | Now U-Boot proper need not get the uniphier_boards array. Compile it only for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor cmd_ddrmphyMasahiro Yamada2017-01-29-83/+112
| | | | | | Make it look like cmd_ddrphy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: clean up UMC init for PXs2 SoCMasahiro Yamada2017-01-29-283/+284
| | | | | | | | | Just cosmetic changes: - Rename prefix DMPHY_ to MPHY_ for consistency - Move UMC parameters below for complete decouple of PHY and UMC - Remove redundant whitespaces Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor cmd_ddrphyMasahiro Yamada2017-01-29-73/+83
| | | | | | | It seems more readable to use arrays to get SoC specific parameters instead of the crappy switch statement. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoCMasahiro Yamada2017-01-29-10/+3
| | | | | | | | | | For LD20 SoC, the last 64 byte of each DRAM bank is used for the dynamic training of DRAM PHY. The regions must be reserved in DT to prevent the kernel from using them. Now gd->bd->bi_dram reflects the actual memory banks. Just use it instead of getting access to the board parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: detect RAM size by decoding HW register instead of DTMasahiro Yamada2017-01-29-49/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot needs to set up available memory area(s) in dram_init() and dram_init_banksize(). It is platform-dependent how to detect the memory banks. Currently, UniPhier adopts the memory banks _alleged_ by DT. This is based on the assumption that users bind a correct DT in their build process. Come to think of it, the DRAM controller has already been set up before U-Boot is entered (because U-Boot runs on DRAM). So, the DRAM controller setup register seems a more reliable source of any information about DRAM stuff. The DRAM banks are initialized by preliminary firmware (SPL, ARM Trusted Firmware BL2, or whatever), so this means the source of the reliability is shifted from Device Tree to such early-stage firmware. However, if the DRAM controller is wrongly configured, the system will crash. If your system is running, the DRAM setup register is very likely to provide the correct DRAM mapping. Decode the SG_MEMCONF register to get the available DRAM banks. The dram_init() and dram_init_banksize() need similar decoding. It would be nice if dram_init_banksize() could reuse the outcome of dram_init(), but global variables are unavailable at this stage because the .bss section is available only after the relocation. As a result, SG_MEMCONF must be checked twice, but a new helper uniphier_memconf_decode() will help to avoid code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoCMasahiro Yamada2017-01-29-175/+79
| | | | | | | | | | | | | The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB memory footprint, which is significant in SPL. There are PHY parameters for 5 boards, but they are actually not board specific, but SoC specific. After all, we just need to have 2 patterns, for LD20 and LD21. Also, the shift values are small enough to become "short" type instead of "int". This change will save about 3 KB memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add PXs3 SoC supportMasahiro Yamada2017-01-22-0/+27
| | | | | | Initial support for PXs3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add macro to generate SoC data look-up functionMasahiro Yamada2017-01-22-33/+23
| | | | | | | | There are similar functions that look up SoC data by the SoC ID. The new macro UNIPHIER_DEFINE_SOCDATA_FUNC will be helpful to avoid the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: simplify SoC ID get functionMasahiro Yamada2017-01-22-317/+214
| | | | | | | | | | Currently, uniphier_get_soc_type() converts the SoC ID (this is read from the revision register) to an enum symbol to use it for SoC identification. Come to think of it, there is no need for the conversion in the first place. Using the SoC ID from the register as-is a straightforward way. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: replace <common.h> with <linux/delay.h> where possibleMasahiro Yamada2017-01-22-4/+5
| | | | | | | | | The <common.h> includes too many headers. Actually, these files needed to include it for udelay() declaration. Now we can replace it with <linux/delay.h> thanks to commit 5bc516ed661a ("delay: collect {m, n, u}delay declarations to include/linux/delay.h"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: replace <linux/err.h> with <linux/errno.h>Masahiro Yamada2017-01-22-14/+16
| | | | | | | | These files only need error number macros. Actually, IS_ERR(), PTR_ERR(), ERR_PTR(), etc. are not useful for U-Boot. Avoid unnecessary header includes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: make SPL optional for ARVv8 SoCsMasahiro Yamada2017-01-22-20/+39
| | | | | | | | | | | | | | | | | | We may want to run different firmware before running U-Boot. For example, ARM Trusted Firmware runs before U-Boot, making U-Boot a non-secure world boot loader. In this case, the SoC might be initialized there, which enables us to skip SPL entirely. This commit removes "select SPL" to make it configurable. This also enables the Multi SoC support for the UniPhier ARMv8 SoCs. (CONFIG_ARCH_UNIPHIER_V8_MULTI) Thanks to the driver model and Device Tree, the U-Boot proper part is now written in a generic way. The board/SoC parameters reside in DT. The Multi SoC support increases the memory footprint a bit, but the U-Boot proper does not have strict memory constraint. This will mitigate the per-SoC (sometimes per-board) defconfig burden. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add missing static and const qualifierMasahiro Yamada2017-01-22-3/+3
| | | | | | These are file-internal and constant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix delay fixup code in LD11 UMC initKotaro Hayashi2017-01-22-0/+1
| | | | | | | | | The ddrphy_shift_rof_hws() never writes back the shifted delay value to the register, which makes this function non-effective. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: add git log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: update UMC_MEMMAPSET value for LD20 SoCWataru Okoshi2017-01-22-2/+2
| | | | | | | Change bnk_typ's value from 8 to 0 (for G1's performance). Signed-off-by: Wataru Okoshi <okoshi.wataru@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move SBC and Support Card init code to U-Boot properMasahiro Yamada2017-01-18-27/+19
| | | | | | | | | | | | | | | Initialize SBC and Support Card in U-Boot proper instead of SPL. We may run different firmware (ex. ARM Trusted Firmware) before U-Boot, and basic SoC initialization may be done there. In that case, SPL may not be used. The motivation for preparing SBC and Support Card in SPL was to use LED for early debugging, but this is not mandatory to boot SoCs. With this commit, LED will be unavailable in SPL, but we can use a debug serial instead. So, this change will not be a big deal. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor spl_init_board()Masahiro Yamada2017-01-18-508/+250
| | | | | | | Merge init-*.c into a single file using a table of callbacks because the initialization flow is almost common among SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor board_init()Masahiro Yamada2017-01-18-95/+141
| | | | | | | The code here is cluttered due to the switch statement. Introduce a table of callbacks to clean up the initialization code across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: make BCU init into void functionMasahiro Yamada2017-01-17-10/+10
| | | | | | These functions never fail, so no need to return a value. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor Support Card init codeMasahiro Yamada2017-01-17-28/+8
| | | | | | | | | | | Splitting reset assertion (support_card_reset) and deassertion (support_card_init) is not adding much value any more. Handle all the initialization of Support Card in support_card_init(), then remove support_card_reset(). Also, detect_num_flash_banks() can have a static qualifier. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor SBC init codeMasahiro Yamada2017-01-17-110/+94
| | | | | | | Merge sbc-admulti.c and sbc-savepin.c into a single file to avoid code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor MEMCONF init codeMasahiro Yamada2017-01-17-259/+176
| | | | | | | | | | | | | | Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code. There are 3 patterns in terms of MEMCONF init: - DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11 - DRAM 3 channels: sLD3 - DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20 All of them can be moved into a single file by a little more refactoring. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: split out UMC clock enableMasahiro Yamada2017-01-17-69/+97
| | | | | | | | The clock enable bits for UMC are more SoC-specific than for the other hardware blocks. Separate the UMC clocks and the other clocks for better code reuse across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unneeded argument of uniphier_ld20_pll_init()Masahiro Yamada2017-01-17-11/+3
| | | | | | | At first, we thought the LD20 PLL setting would be board dependent, but this argument turned out unneeded after all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-12-12-5/+7
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| * ARM: uniphier: remove unneeded parenthesesMasahiro Yamada2016-12-10-3/+3
| | | | | | | | | | | | Just a cosmetic cleanup. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: remove unneeded initializerMasahiro Yamada2016-12-10-2/+4
| | | | | | | | | | | | This will be used to store the return value of readl(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | spl: uniphier: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-5/+0
| | | | | | | | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | spl: Add a name to the SPL load-image methodsSimon Glass2016-12-09-1/+1
|/ | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: update DRAM init code for LD11 SoCMasahiro Yamada2016-10-29-23/+391
| | | | | | Introduce run-time DDR PHY training. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support DDR PHY parameter dump command for LD11Masahiro Yamada2016-10-29-6/+19
| | | | | | | | Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor DDR PHY parameter dump commandMasahiro Yamada2016-10-29-44/+50
| | | | | | | | | | Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoCMasahiro Yamada2016-10-29-294/+302
| | | | | | | | | The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-01 10:40:02 +0000